Technology License Agreement

A.

LICENSEE has requested ARM and ARM has agreed to license LICENSEE to manufacture and distribute certain ARM Secure Core Based Products (as defined below) on the following terms and conditions.

B.

Therefore, in consideration of the mutual representations, warranties, covenants, and other terms and conditions contained herein, the parties agree as follows:

1.

Definitions

1.1

“ ARM Secure Core ” means the ARM Secure Core identified in the Technical Reference Manual [DDI-0207-A].

1.2

“ ARM Secure Core Synthesizable Source ” means together; (i) the Synthesizable RTL; (ii) the Synthesis Scripts; and (iii) the Synthesis Reference Deliverables.

1.3

“ ARMv4T Instruction Sets ” means both the ARMv4 instruction set and Thumb instruction set as defined in the ARM Architecture Reference Manual [ARM DDI 0100].

1.4

“ ARM Secure Core Transfer Materials ” means together; (i) the ARM Secure Core Synthesizable Source; (ii) the Implementation Guide; (iii) the Synthesizable Functional Test Vectors; (iv) the Technical Reference Manual; (v) the AVS; (vi) the Core Self Test Programs, together with any Updates thereto delivered to LICENSEE by ARM from time to time; and (vii) any relevant supplemental documentation released by ARM to its other licensees from time to time.

1.5

“ ARM Secure Core Based Product(s) ” means any chip designed and manufactured by or for LICENSEE which is offered for sale solely for use in applications where secure processing is specified and which contains at a minimum; (i) a Microarchitecture Compliant Core; and (ii) LICENSEE or LICENSEE’s customer’s circuitry which adds significant functionality.

1.6

“ ARM Transfer Materials ” means together; (1) the ARM Secure Core Transfer Materials; and (ii) the MME Transfer Materials.

1.7

“ Authorized Distributor ” means any distributor appointed, in writing, by LICENSEE.

1.8

“ AVS ” means the ARM architectural validation suite identified in Schedule 1 Part H.

1.9

“ Claim ” means a written notice of infringement received by ARM from a third party demanding that ARM cease and desist from such alleged Intellectual Property infringement.

1.10

“ Confidential Information ” means; (i) any trade secrets relating to the ARM Secure Core and the ARM Transfer Materials; (ii) any information designated in writing by either party, by appropriate legend, as confidential; (iii) any information which if first disclosed orally is identified as confidential at the time of disclosure and is thereafter reduced to writing for confirmation and sent to the other party within thirty (30) days after its oral disclosure and designated, by appropriate legend, as confidential; and (iv) the terms and conditions of this Agreement.

1.11

“ Core Self Test Programs ” means the programs identified in Schedule 1 Part K Item K1.

1.12

“ Documentation ” means the documentation identified in Schedule 2 Part A.

1.13

“ Effective Date ” means the date of this Agreement, subject always to the provisions of Clause 15.13.

1.14

“ End User License ” means a license agreement substantially in the form set out in Schedule 6.

1.15

“ Implementation Guide ” means the documentation identified in Schedule 1 Part B.

1.16

“ Intellectual Property ” means any patents, patent rights, trade marks, service marks, registered designs, topography or semiconductor maskwork rights, applications for any of the foregoing, copyright, unregistered design right, trade secrets and know-how and any other similar protected rights in any country.

1.17

“ LICENSEE’s Synthesis Timing Constraints File ” means such timing constraints file as the LICENSEE shall finalise prior to final synthesis.

1.18

“ Microarchitecture Compliant Core ” means an implementation of an ARM Secure Core manufactured under licence from ARM and which:

(i)

executes each and every instruction in the ARMv4T Instruction Sets;

(ii)

executes no additional instructions to those contained in the ARMv4T Instruction Sets;

(iii)

exhibits a Pipeline Length of 3;

(iv)

exhibits a Von Neumann Architecture;

(v)

is Single Issue or Multiple Issue, as appropriate for the respective ARM Secure Core as identified in the relevant Technical Reference Manual;

(vi)

implements the programmer’s model as identified in the ARM Architecture Reference Manual;

(vii)

passes the respective Synthesizable Functional Test Vectors; and

(viii)

has been verified in accordance with the provisions of Clause 3.

1.19

“ MME Macrocell ” means the MME hardware accelerator specified in the MME Technical Reference manual SC043-TRM-0001-A.

1.20

“ MME Synthesizable RTL ” means the deliverable identified in Schedule 2 Part B Section 1.

1.21

“ MME Synthesis Scripts ” means the deliverables identified in Schedule 2 Part B Section 2.

1.22

“ MME Synthesizable Source ” means together, (i) the MME Synthesizable RTL; and (ii) the MME Synthesis Scripts.

1.23

“ MME Transfer Materials ” means together (i) the MME Synthesizable Source; (ii) the MME Validation Suite; (iii) the Documentation; (iv) the Software, together with any Updates thereto delivered to LICENSEE by ARM from time to time; and (iv) any relevant supplemental documentation released by ARM to licensees from time to time.

1.24

“ NSP ” means the net sales price of any ARM Secure Core Based Product calculated by taking the aggregate invoice price charged on arms length terms by LICENSEE and its Subsidiaries in the sale or distribution of any ARM Secure Core Based Product, less any; (i) value added, turnover, import, or other tax, duty or tariff payable thereon; (ii) freight, insurance costs incurred; and (iii) amounts actually repaid or credited with respect to any ARM Secure Core Based Products returned.

1.25

“ MME Validation Suite ” means the deliverables identified in Schedule 2 Part C.

1.26

“ Packaging ” means the materials used to encapsulate the silicon of an ARM Secure Core Based Product.

1.27

“ Pipeline Length ” means the number of clocked stages through which each single-cycle instruction must pass to complete the execution of such instruction.

1.28

“ Single Issue ” means that only one instruction is issued for execution within the integer unit in any single clock cycle (where for the purposes of this definition “clock” means the clock that advances the pipeline).

1.29

“ Software ” means the example support software for the MME Macrocell as identified in Schedule 2 Part D, together with any Updates thereto delivered to LICENSEE by ARM from time to time.

1.30

“ Subsidiary ” means any company the majority of whose voting shares is now or hereafter owned or controlled, directly or indirectly, by a party hereto or any company a majority of whose voting shares is now or hereafter owned or controlled, directly or indirectly, by any of the aforementioned entities. The company shall be considered a Subsidiary only so long as such control exists.

1.31

“ Synthesizable Functional Test Vectors ” means the synthesizable functional test vectors identified in Schedule 1 Part D.

1.32

“ Synthesis Reference Deliverables ” means the deliverables identified in Schedule 1 Part C Section 3.

1.33

“ Synthesizable RTL ” means the deliverables identified in Schedule 1 Part C Section 1.

1.34

“ Synthesis Scripts ” means the deliverables identified in Schedule 1 Part C Section 2.

1.35

“ Technical Reference Manual ” means the technical reference manual identified in Schedule 1 Part A.

1.36

“ Trademarks ” means the trademarks identified in Schedule 3.

1.37

“ Updates ” means any enhancements and modifications including but not limited to any error corrections to the ARM Transfer Materials including any documentation associated therewith, designed by, or for ARM, the incorporation of which ARM, in its absolute discretion, decides does not cause a new product to be created.

1.38

“ Unique ARM Secure Core Based Product ” means a device manufactured by or for LICENSEE and which has a unique part number; except that a device shall not be a Unique ARM Secure Core Based Product if the device has a different part number for any or all of the following reasons:

(i)

because it is an optically shrunk version of an otherwise unmodified (except to the extent accommodated by this definition) Unique ARM Secure Core Based Product;

(ii)

because it is a version of an otherwise unmodified (except to the extent accommodated by this definition) Unique ARM Secure Core Based Product that has been ported to a different set of process design rules;

(iii)

because it is an otherwise unmodified (except to the extent accommodated by this definition) Unique ARM Secure Core Based Product that has a different on chip memory size;

(iv)

because it is an otherwise unmodified (except to the extent accommodated by this definition) Unique ARM Secure Core Based Product that has a different on chip memory content;

(v)

because it is an otherwise unmodified (except to the extent accommodated by this definition) Unique ARM Secure Core Based Product that has a different on chip memory type;

(vi)

because it is an otherwise unmodified (except to the extent accommodated by this definition) Unique ARM Secure Core Based Product that incorporates a bug fix (to conform to original specification for the Unique ARM Secure Core Based Product); and

(vii)

because it is an otherwise unmodified (except to the extent accommodated by this definition) Unique ARM Secure Core Based Product that incorporates a different revision of the ARM Transfer Materials delivered by ARM to LICENSEE from time to time.

1.39

“ Von Neumann Architecture ” means a microprocessor architecture which dictates that the instruction stream for the integer unit shares the same port with the data stream for such integer unit.

2.

Licence

2.1

Subject to the provisions of Clause 9 (Confidentiality) and the payment of appropriate fees in accordance with the provisions of Clause 5, ARM hereby grants to LICENSEE, under ARM’s Intellectual Property, a non-transferable (subject to Clause 15.3), non-exclusive, perpetual (subject to termination in accordance with the provisions of Clause 13) world-wide licence, to;

(i)

use and copy the AVS and the MME Validation Suite only for the purposes of designing ARM Secure Core Based Products;

(ii)

use, copy and modify the Core Self Test Programs only for the purposes of designing ARM Secure Core Based Products;

(iii)

use and copy; (a) the Implementation Guide; and (b) the Synthesisable Reference Deliverables, only for the purposes of designing ARM Secure Core Based Products;

(iv)

use, copy and modify (solely to the extent necessary to run the following deliverables on LICENSEE’s tester or simulator) the Synthesizable Functional Test Vectors, only for the purposes of designing ARM Secure Core Based Products;

(v)

use, copy and modify (only for the purpose of substituting functional blocks in the Synthesizable RTL with functionally equivalent LICENSEE or LICENSEE’s customer’s functional blocks); (i) the Synthesizable RTL; and (ii) the MME Synthesizable RTL, only for the purposes of designing ARM Secure Core Based Products;

(vi)

use, copy and modify; (i) the Synthesis Scripts; and (ii) the MME Synthesis Scripts, only for the purposes of designing ARM Secure Core Based Products;

(vii)

manufacture and have manufactured (subject to the provisions of Clause 2.2) the ARM Secure Core Based Products created under the licences granted in Clauses 2.1(i) to 2.l(vi) inclusive;

(viii)

sell, supply and distribute ARM Secure Core Based Products manufactured under the licences granted in Clause 2.1(vii) to any third party and authorise Authorised Distributors to do the same;

(ix)

test and have tested (subject to the provisions of Clause 2.3) the ARM Secure Core Based Products manufactured under the licences granted in Clause 2.1(vii);

(x)

use, copy, modify and distribute (solely to LICENSEE’s customers of ARM Secure Core Based Products and subject to the terms of a confidentiality agreement no less restrictive than those contained in this Agreement) the Technical Reference Manual only for the purposes of designing ARM Secure Core Based Products;

(xi)

use, copy, modify and distribute (solely to LICENSEE’s customers of ARM Secure Core Based Products and subject to the terms of a confidentiality agreement no less restrictive than those contained in this Agreement) the Documentation only for the purposes of designing ARM Secure Core Based Products;

(xii)

 use, copy and modify the Software; and

(xiii)

 distribute the Software in source code or binary code form solely in conjunction with ARM Secure Core Based Products.

2.2

Subject to the provisions of Clause 9 (Confidentiality), LICENSEE may exercise its right to have ARM Secure Core Based Products manufactured by a third party manufacturer (“ Manufacturer ”) in accordance with the provisions of Clause 2.1 solely to manufacture ARM Secure Core Based Products for LICENSEE provided that; (a) LICENSEE agrees not to grant to the Manufacturer any license in respect of any ARM Transfer Materials for any other purpose; and (b) that each Manufacturer agrees;

(i)

to be bound by obligations of confidentiality no less restrictive than those contained in this Agreement;

(ii)

to supply units of the ARM Secure Core Based Product solely to LICENSEE; and

(iii)

to return any ARM Confidential Information and ARM Transfer Materials to LICENSEE on the earlier of; (a) the completion of the manufacture; and (b) the expiration of the

confidentiality period for each ARM Transfer Material in accordance with the provisions of Clause 9.

2.3

Subject to the provisions of Clause 9 (Confidentiality), LICENSEE may exercise its right to have ARM Secure Core Based Products tested by a third party (“ Test House ”) in accordance with the provisions of Clause 2.1 provided that the Test House agrees:

(i)

to be bound by obligations of confidentiality no less restrictive than those contained in this Agreement; and

(ii)

to supply units of the tested ARM Secure Core Based Products solely to LICENSEE; and

(iii)

to return any ARM Confidential Information and ARM Transfer Materials to LICENSEE on the earlier of; (a) the completion of the test; and (b) the expiration of the confidentiality period for each ARM Transfer Material in accordance with the provisions of Clause 9.

2.4

On receipt of a request from LICENSEE, ARM may on a case by case basis grant LICENSEE the right to have ARM Secure Core Based Products designed by a designer subcontracted by LICENSEE (“ Designer ”) provided that each Designer agrees;

(i)

to be bound by obligations of confidentiality no less restrictive than those contained in this Agreement; and

(ii)

to supply units of the tested ARM Secure Core Based Products solely to LICENSEE; and

(iii)

to return any ARM Confidential Information and ARM Transfer Materials to LICENSEE on the earlier of; (a) the completion of the design; and (b) the end of the confidentiality period for each ARM Transfer Material in accordance with the provisions of Clause 9.

2.5

No right is granted to LICENSEE to:

(i)

except as expressly granted in Clauses 2.1, sub-license any of the rights licensed to LICENSEE under Clause 2.1; or

(ii)

distribute any ARM Secure Core Based Product prior to verification in accordance with Clause 3, except that if it is the intention of LICENSEE, and LICENSEE does proceed, to verify a device in accordance with Clause 3.1 and 3.2, LICENSEE may distribute, in aggregate, up to two thousand (2000) prototype units of such device without having such devices verified provided that LICENSEE provides written evidence to ARM that; (a) the recipient of such devices is aware that such device has not passed the verification process by ARM; and (b) the recipient has agreed to keep the recipient’s use of the non verified device as confidential.

2.6

Except as specifically licensed in Clause 2.1, LICENSEE acquires no right, title or interest in the ARM Secure Cores, ARM Transfer Materials or any of ARM’s Intellectual Property embodied therein. In no event shall the License grant set out in Clause 2.1 be construed as granting LICENSEE, expressly or by implication, estoppel or otherwise, a license to use any ARM technology except the ARM Transfer Materials arid Software. LICENSEE shall reproduce and not remove or obscure any notice incorporated in the ARM Transfer Materials by ARM to protect ARM’s Intellectual Property or to acknowledge the copyright and/or contribution of any third party designer. LICENSEE shall incorporate corresponding notices and/or such other markings and notifications as ARM may reasonably require on all copies of the ARM Transfer Materials used or distributed by LICENSEE.

2.7

For the continuance of this Agreement, LICENSEE may exercise the right to include any Subsidiary as a licensee under the terms of this Agreement provided that;

(i)

such Subsidiary agrees in writing, as set out in Schedule 10 to be bound by the obligations of LICENSEE and to comply with all the terms and conditions of this Agreement;

(ii)

any breach of the terms and conditions of this Agreement by a Subsidiary shall constitute a breach of this Agreement by LICENSEE; and

(iii)

any termination of this Agreement in accordance with the provisions of Clause 13 shall be effective in respect of all Subsidiaries.

3.

Verification

3.1

For each ARM Secure Core implementation which is used in the manufacture of ARM Secure Core Based Products for sale and distribution by LICENSEE in accordance with the terms of this Agreement, LICENSEE shall in the course of generating such implementation use the ARM Transfer Materials to generate a netlist (each a “ Synthesized Netlist ”) which includes back-annotated delays derived from the physical layout of the Synthesized Netlist.

3.2

LICENSEE shall simulate the AVS on each Synthesized Netlist (defined in Clause 3.1).

3.3

LICENSEE shall deliver to ARM a copy of the log results generated by running the AVS on each respective Synthesized Netlist (the “ Synthesized Log Results ” for each Synthesized Netlist). Prior to delivery of such Synthesized Log Results LICENSEE shall give ARM as much advance warning as practicably possible of LICENSEE’S proposed delivery of such Synthesized Log Results.

3.4

Each Synthesized Netlist shall be verified for a particular process upon ARM’S acceptance of the Synthesized Log Results delivered by LICENSEE.

3.5

The Synthesized Log Results shall be accepted when they indicate that no errors have been detected or where any errors detected have been jointly agreed, in good faith, and a waiver agreed between the parties.

3.6

ARM shall notify LICENSEE, in writing, within fifteen (15) days of delivery by LICENSEE of the Synthesized Log Results (“ Synthesis Verification Period ”), whether the Synthesized Log Results have been accepted by ARM or have failed the in verification process. In the event that ARM fails to confirm the result of the verification process within the Synthesis Verification Period, the Synthesized Log Results shall be deemed accepted by ARM. In the event that the Synthesized Log Results fail the verification process, ARM shall provide details of the errors which cause the failure to LICENSEE and LICENSEE shall endeavour to correct the errors. The parties shall repeat the above process until either; (i) the Synthesized Log Results are accepted; or (ii) LICENSEE wit