WAFER SUPPLY AGREEMENT

Exhibit 10.5

WAFER SUPPLY AGREEMENT

This W AFER S UPPLY A GREEMENT (this “ Agreement ”) is made this 2nd day of March, 2009, (the “ Effective Date ”), by and among (i) Advanced Micro Devices, Inc . , a Delaware corporation (“ AMD ”); (ii) with respect to all of the provisions in this Agreement other than those in Sections 5.5(a), 6.2, 7.1 and 7.3(a) and the related provisions in connection with U.S. sales activities only (though without limiting FoundryCo’s guarantee obligations pursuant to Section 15.7), The Foundry Company, an exempted company incorporated under the laws of the Cayman Islands (“ FoundryCo ”) on behalf of itself and its direct and indirect wholly-owned subsidiaries, including all FoundryCo Sales Entities and FoundryCo Manufacturing Entities, as further set forth herein; and (iii) subject to FoundryCo’s guarantee obligations pursuant to Section 15.7, with respect to Sections 5.5(a), 6.2, 7.1 and 7.3(a) and the related provisions in connection with U.S. sales activities only, AMD Fab Technologies US, Inc., a Delaware corporation and a wholly-owned subsidiary of FoundryCo ( “USOpCo” ).

WHEREAS, AMD has been in the business of designing and manufacturing semiconductor products;

WHEREAS, AMD desires to transfer its business of manufacturing and sorting semiconductor products to FoundryCo pursuant to the Master Transaction Agreement by and among AMD, Advanced Technology Investment Company LLC and West Coast Hitech L.P., dated as of October 6, 2008 (as may be amended from time to time, the “ Master Agreement ”);

WHEREAS, it is the intent of the parties that this Agreement establish a productive, mutually-beneficial relationship among the parties that will mitigate key risks for each party by establishing volume, capacity and pricing commitments by each party pursuant to the terms and conditions set forth herein;

WHEREAS, the parties also desire that this Agreement help establish business processes for the parties to work closely together on planning capacity and supply;

WHEREAS, FoundryCo is a company whose primary purpose is the provision of wafer fabrication foundry services and FoundryCo is willing to provide such services to AMD on the terms and conditions set forth herein, and AMD is willing to engage FoundryCo to provide foundry services to AMD on the terms and conditions set forth herein; and

WHEREAS, all purchases of Products by AMD will be made from FoundryCo Sales Entities, including USOpCo, and all manufacturing of Products for AMD will be performed by FoundryCo Manufacturing Entities;

NOW, THEREFORE, in consideration of the mutual promises of the parties, and of good and valuable consideration, it is agreed by and among the parties as follows:

1. DEFINITIONS

For the purpose of this Agreement the following capitalized terms are defined in this Section 1 and shall have the meaning specified herein. Other terms that are capitalized but not specifically defined below or in this Agreement shall have the meaning set forth in the Master Agreement.

1.1 “Actual Quarterly GPU Wafers Shipped” shall mean the actual number of Wafer Outs for GPU Products delivered in a fiscal quarter from the applicable FoundryCo Sales Entities to AMD.

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

1.2 “Actual Quarterly Total GPU Wafer Demand” shall mean the actual number of Wafer Outs for GPU Products delivered in a fiscal quarter from all foundry partners to AMD.

1.3 “Actual Quarterly GPU Wafer Demand Percentage” is calculated as Actual Quarterly GPU Wafers Shipped divided by Actual Quarterly Total GPU Wafer Demand.

1.4 “AMD Furnished Property” shall mean materials or tooling that AMD consigns to the applicable FoundryCo Manufacturing Entities for use by the applicable FoundryCo Manufacturing Entities to process AMD’s Product orders or to perform services on AMD’s behalf, as further set forth in this Agreement, including such materials or tooling (other than Sort Equipment owned by the applicable FoundryCo Manufacturing Entities on the Effective Date pursuant to the Master Agreement) required by the FoundryCo Manufacturing Entities to provide Sort Services pursuant to the terms of this Agreement.

1.5 “AMD Indemnified Parties” shall have the meaning set forth in Section 10.2.

1.6 “AMD MPU Specific Development Wafer Cost” shall mean the sum of:

(a) During a Period, the number of Development Wafer Starts for MPU Products multiplied by the AMD MPU Specific Direct Material Cost, divided by the sum of the number of Production Wafer Starts for MPU Products and the number of Development Wafer Starts of MPU Products, which, in an equation format, shall be:

 

 

(b) During such Period, (i)(1) the number of Development Wafer Starts for MPU Products multiplied by the Development Factor and then multiplied by (2) the AMD MPU Specific Manufacturing Costs less the AMD MPU Specific Direct Material Cost, divided by (ii) the sum of (1) the number of Production Wafer Starts for MPU Products and (2) the number of Development Wafer Starts for MPU Products multiplied by the Development Factor, which, in an equation format, shall be:

 

 

1.7 “AMD MPU Specific Direct Material Cost” shall mean the actual cost of Raw Wafers for MPU Products.

1.8 “AMD MPU Specific Fixed Cost” shall mean all AMD MPU Specific [****] actually incurred during a Period, other than the AMD MPU Specific [****]. For the avoidance of doubt and notwithstanding anything to the contrary, AMD MPU Specific Fixed Cost shall include, and AMD shall pay, [****] for the [****] existing on the Effective Date (which shall be [****] in [****] and [****] in [****]) and [****] for the [****] to be put in [****] to [****] AMD MPU Product [****], and agreed to by the parties, pursuant to Sections 2.2 and 5.1 that have not been recouped by the applicable FoundryCo Manufacturing Entities.

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

1.9 “AMD MPU Specific Inventory Change” shall mean the amount calculated by subtracting (a) the gross inventory dollars attributable to MPU Products manufactured for AMD at the end of a relevant Period from (b) the gross inventory dollars attributable to MPU Products manufactured for AMD at the beginning of such Period (excluding, in each case, Raw Wafers).

1.10 “AMD MPU Specific Manufacturing Costs” shall mean all [****] and [****] costs incurred in the MPU Product wafer manufacturing process (including [****] Services Cost and [****] cost (which shall include [****] on [****] owned by the FoundryCo Manufacturing Entities on the Effective Date), and whether or not such wafers are [****] and whether or not such wafers are [****] or are in [****]) and which would properly be included according to industry and accounting standards in the cost of a [****], [****] or a [****]. AMD MPU Specific Manufacturing Costs shall not include [****], nor shall it include [****] or [****] and [****]. AMD MPU Specific Manufacturing Costs shall be equal to the sum of AMD MPU Specific [****] and AMD MPU Specific [****]. In addition, AMD MPU Specific Manufacturing Costs shall be equal to the sum of AMD MPU Specific [****] and AMD MPU Specific [****].

1.11 “AMD MPU Specific Other COGS” shall mean FoundryCo’s allocation of other costs of goods sold related to MPU Products not otherwise specified as AMD MPU Specific [****], as determined in accordance with industry and accounting standards as generally applied by FoundryCo, and which includes as of the Effective Date a portion of the [****] of [****] related [****], a portion of the [****] of the [****] organization (mostly within the sub-organization [“****,”] which is almost entirely [****]), a portion of the [****] related to [****], as well as a portion of other costs (including certain [****] allocated to COGS) that are incurred in direct support of the [****] in the FoundryCo Manufacturing Entities’ facilities.

1.12 “AMD MPU Specific Production Wafer Cost ” shall mean the sum of:

(a) During a Period, the number of Production Wafer Starts for MPU Products multiplied by the actual AMD MPU Specific Direct Material Cost, divided by the sum of the number of [Production Wafer Starts for MPU Products and the number of Development Wafer Starts for MPU Products, which, in an equation format, shall be:

 

 

; and

(b) During such Period, (i)(1) the number of Production Wafer Starts for MPU Products multiplied by (2) the AMD MPU Specific Manufacturing Costs less the AMD MPU Specific Direct Material Cost, divided by (ii) the sum of (1) the number of Production Wafer Starts for MPU Products and (2) the number of Development Wafer Starts for AMD MPU Products multiplied by the Development Factor, which, in an equation format, shall be:

 

 

1.13 “AMD MPU Specific Total COGS” shall mean the sum of AMD MPU Specific Production Wafer Cost, AMD MPU Specific Other COGS and AMD MPU Specific Inventory Change.

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

1.14 “AMD MPU Specific Variable Cost” shall mean those AMD MPU Specific Manufacturing Costs actually incurred during a Period, consisting of AMD MPU Specific Direct Materials Cost, and [****] percent ([****]%) of [****].

1.15 “AMD-Specific Engineering Expense Allocation” shall mean the actual costs incurred by FoundryCo Manufacturing Entities in developing AMD-Specific Manufacturing Process Technologies.

1.16 “AMD-Specific License Fee Allocation” shall mean [****] percent ([****]%) of the aggregate [****] fees incurred by FoundryCo according to the [****] and [****] between [****] and AMD dated as of [****], as may be amended from time to time, for both [****] and [****] process technologies, and [****] percent ([****]%) of any additional licenses required specifically for MPU Products.

1.17 “AMD-Specific Manufacturing Process Technology” shall refer to any manufacturing or sorting process technology used at the time of development by any FoundryCo Manufacturing Entity specifically for AMD. For purposes of example only, as of the Effective Date, the [****] is currently considered an AMD-Specific Manufacturing Process Technology. For the avoidance of doubt, [****] process technology, unless specifically designed to manufacture only Products, is not an AMD-Specific Manufacturing Process Technology.

1.18 “AMD-Specific Process Engineering Wafer Starts” shall mean the Wafer Starts of AMD-Specific Process Engineering Wafers.

1.19 “AMD-Specific Process Development Wafers” or “AMD-Specific Process Engineering Wafers” shall mean Process Engineering Wafers processed by a FoundryCo Manufacturing Entity utilizing an AMD-Specific Manufacturing Process Technology.

1.20 “AMD-Specific Process Engineering Wafer Cost” shall mean the portion of AMD MPU Specific Development Wafer Costs incurred to produce AMD-Specific Process Engineering Wafers. It shall be determined based on the ratio of AMD-Specific Process Engineering Wafer Starts] to Development Wafer Starts (for MPU Products).

1.21 “AMD-Specific Product Qualification Plan” shall mean the qualification tests and schedules to be agreed upon by the parties under which a Product is Qualified.

1.22 “AMD-Specific Qualification Plan” shall mean the qualification tests and schedules to be agreed upon by the parties under which an AMD-Specific Qualified Process is established and tested at the applicable FoundryCo Manufacturing Entity and the MPU Products are manufactured using an AMD-Specific Qualified Process to meet the Specifications.

1.23 “AMD-Specific Qualified Process” shall mean the wafer manufacturing processes used at the applicable FoundryCo Manufacturing Entity specifically for production of Wafers for AMD with respect to MPU Products, and any other FoundryCo-proprietary wafer manufacturing process approved by the parties specifically to produce MPU Products on AMD’s behalf.

1.24 “AMD-Specific R&D Costs” shall mean the sum of AMD-Specific [****], AMD-Specific [****] and AMD-Specific [****].

1.25 “[ **** ]” shall mean the [****] of the applicable FoundryCo Manufacturing Entities’ [****] to [****] the [****] of (a) any [****] within the FoundryCo Manufacturing Entities and (b) any [****] to AMD.

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

1.26 “Binding Forecast” shall mean AMD’s MPU Product forecast for the first [****] months of any rolling [****] month MPU Product forecast as set forth in Section 5.1 and in accordance with Section 2.2. For the avoidance of doubt, a “Binding Forecast” shall not include any forecast that requires more capacity to manufacture the relevant Products than the capacity that had been agreed upon pursuant to Section 2.2.

1.27 “Binding Forecast Period” shall mean the first [****] months of any rolling [****] month MPU Product forecast.

1.28 “ [ **** ] ” shall have the meaning set forth in Section 2.1(b)(i).

1.29 “ [ **** ] Change of Control Transaction ” shall mean a transaction with or among [****] or any of its subsidiaries and any other person (other than FoundryCo) with respect to (a) a merger, consolidation, business combination or similar transaction of [****], (b) any purchase of an equity interest (including by means of a tender or exchange offer) representing an amount equal to or greater than a [****] percent ([****]%) voting or economic interest in [****], or (c) any purchase of assets, securities or ownership interests representing an amount equal to or greater than [****] percent ([****]%) of the consolidated assets of [****] and its subsidiaries taken as a whole (including stock of [****]’s subsidiaries); provided that a sale or transfer of assets that are not used to manufacture on behalf of [****] shall not be included in the calculation of assets to determine a [****] Change of Control Transaction.

1.30 “COGS” shall mean cost of goods sold in accordance with AMD’s standard practices in effect as of the Effective Date.

1.31 “Confidential Information” shall mean all proprietary or nonpublic information disclosed by one party to another party in connection with this Agreement, whether in graphic, oral, written or electronic form, directly or indirectly, which information (a) is marked as “proprietary” or “confidential” or, if disclosed orally, is designated as confidential or proprietary at the time of disclosure, or (b) provided under circumstances reasonably indicating that it constitutes confidential and proprietary information.

1.32 “Development Factor” shall mean a factor calculated once per fiscal year (within the first fiscal quarter of a year for application to that fiscal year) by FoundryCo to reflect [****] for processing [****] versus a [****] Wafer. The Development Factor is used for the [****] of AMD MPU Specific [****] for a Period into AMD MPU Specific [****] and AMD MPU Specific [****]. The Development Factor consists of a factor for [****] and a factor for [****] that are consolidated into one factor (weighted with the [****] of the respective [****] categories). The development factor for [****] reflects the higher effort due to engineering times before, during and after processing [****], e.g. creation of ERFs, writing reports, R&D-analysis, and split lots. The calculation is based on [****] via [****] for representative ERFs and on processing data of the ERFs in the manufacturing execution system (currently [****]). The development factor for [****] reflects the [****] for [****] versus a [****]. The data is collected and calculated through a software tool. Output of this software tool is per [****] per [****] versus [****] per [****] over [****]. This [****] will be weighted with the running [****] per [****]. As of the Effective Date, the Development Factor is [****].

1.33 “Development Wafer Starts” shall mean the combined Wafer Starts of AMD-Specific Process Engineering Wafers and Product Development Wafers.

1.34 “Die” shall mean one of the semiconductor devices on a Wafer produced by FoundryCo for AMD using a Qualified Process.

1.35 “Dispute” shall have the meaning set forth in Section 15.11(b).

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

1.36 “Dispute Notice” shall have the meaning set forth in Section 15.11(b).

1.37 “Embedded Products” shall mean x86-based semiconductor devices or any other device based on new architecture or architecture adopted in the future, in each case, other than MPU Products that are used in systems that have targeted applications, and which are not designed for use as central processing units for general purpose desktop, notebook, workstation, server computers or game consoles. Embedded Products shall include AMD’s Geode™ product lines.

1.38 “Engineering Change” shall mean any change to the process, materials, equipment, technology, location or any other items listed in FoundryCo’s standard specifications for which a change would affect the performance, function or reliability of the Wafers.

1.39 “Engineering Request Form” or “ERF” shall mean an engineering request form submitted by AMD to FoundryCo to carry out an experiment in a process line.

1.40 “Engineering Wafers” shall mean those Wafers required for the Qualification Plan or delivered to AMD for testing pursuant to AMD’s request. Engineering Wafers consist of Process Development Wafers and Product Development Wafers.

1.41 “Epidemic Failure” shall mean the occurrence of an average in-field failure rate of [****] percent ([****]%) or more per month of the total units for a particular Product delivered in any rolling [****] month period.

1.42 “Fab Start up Costs” shall mean the costs required by FoundryCo to establish new facilities or to convert existing facilities to new wafer sizes (e.g., from 200mm to 300mm) and any other costs which FoundryCo would otherwise include in this category.

1.43 “Forecasted GPU Wafer Demand” shall mean a non-binding, rolling [****] month forecast describing the monthly Wafer Outs expected to be placed by AMD on FoundryCo Sales Entities for GPU Products.

1.44 “Forecasted Total GPU Wafer Demand” shall mean a non-binding, rolling [****] month forecast describing the total Wafer Outs expected to be placed by AMD on all foundry partners for GPU Products.

1.45 “Forecasted GPU Wafer Demand Percentage” is calculated as Forecasted GPU Wafer Demand divided by Forecasted Total GPU Wafer Demand.

1.46 “FoundryCo Indemnified Parties” shall have the meaning set forth in Section 10.1.

1.47 “FoundryCo Manufacturing Entities” shall mean FoundryCo and any direct or indirect wholly-owned subsidiaries of FoundryCo to which FoundryCo has delegated the responsibility to manufacture Products for AMD in accordance with this Agreement.

1.48 “FoundryCo Sales Entities” shall mean USOpCo and any other direct or indirect wholly-owned subsidiaries of FoundryCo to which FoundryCo has delegated the responsibility to process purchase orders from AMD and to offer to sell and sell Products to AMD in accordance with this Agreement.

1.49 “Fusion Products” shall mean both (a) MPU Products that incorporate GPU Products and (b) GPU Products that incorporate MPU Products; for purposes hereof, subsection (iv) of the “MPU Products” definition referring to “Fusion Products” shall not apply.

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

1.50 “GAC” shall mean gases, acids and chemicals.

1.51 “G&A Expenses” shall mean standard general and administrative expenses, as calculated by FoundryCo in accordance with accounting standards as generally applied by FoundryCo.

1.52 “ GPU Minimum Percentage ” shall have the meaning set forth in Section 2.1(c)(ii).

1.53 “GPU Product” shall mean an integrated or discrete graphics processing unit. As an example, as of the Effective Date, GPU Products consist of integrated or discrete graphics processing unit for use in any of the following or similar products: desktop computers, notebook computers, servers, workstations or game consoles.

1.54 “Interim Relief Proceeding” shall have the meaning set forth in Section 15.11(c).

1.55 “Lead Time” shall mean the time between the date an order is accepted by a FoundryCo Sales Entity and the date the Wafers are made available for shipment by the FoundryCo Sales Entity.

1.56 “Major Change” shall mean a change to a manufacturing process that would affect the form, fit, or function of a Product of AMD or that otherwise materially affects a manufacturing process for AMD.

1.57 “ Minimum Batch Size ” shall mean the minimum total number of Wafers in a Process Batch for a particular Product.

1.58 “MPU Products” shall mean any of the following: (i) the x86, x86-64, and IA (Intel Architecture)-64 families of microprocessors, (ii) any existing or new microprocessors based on the x86, x86-64, and IA-64 family architecture, or any new instruction set for a processor described in clause (i) first introduced by AMD, (iii) any microprocessors based on new architecture or an architecture adopted in the future, or (iv) Fusion Products. As used in this definition, a microprocessor shall include a component that can execute computer programs and is the central processing unit controlling an electronic device.

1.59 “Other Future Products” shall mean any future integrated circuit devices designed by AMD other than GPU Products and MPU Products.

1.60 “Partnership Committee” shall have the meaning set forth in Section 3.2(a).

1.61 “Period” shall mean a fiscal month or fiscal quarter, as applicable to the specific measurement period in question.

1.62 “ Process Batch ” shall mean a group of wafers that are processed together as a group.

1.63 “Process Development Wafers” or “Process Engineering Wafers” shall mean Engineering Wafers produced by a FoundryCo Manufacturing Entity to enable it to design, develop, establish, test, improve and validate FoundryCo Manufacturing Entity manufacturing processes. For avoidance of doubt, Process Development Wafers or Process Engineering Wafers shall not include Engineering Wafers expressly requested by AMD, which shall be counted as Product Development Wafers.

1.64 “Process Node” shall mean a specific geometry loosely based on minimum line width at which semiconductor integrated circuit devices, and the photomasks or reticles used in the manufacture of those devices, are manufactured (e.g., a 45 nm process node). For avoidance of doubt, Process Nodes shall include half nodes (e.g., 40nm and 28nm process nodes).

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

1.65 “Product” shall mean an integrated circuit device incorporating AMD’s proprietary designs to be manufactured by the FoundryCo Manufacturing Entities and sold to AMD by the FoundryCo Sales Entities, including Embedded Products, GPU Products, MPU Products and Other Future Products. The Products will be provided to AMD as unprobed Wafers, probed Wafers or bumped Wafers, as specified in the applicable purchase order.

1.66 “Product Development Wafers” shall mean Engineering Wafers requested by AMD and produced by the FoundryCo Manufacturing Entities to test, evaluate and validate Product designs, including, but not limited to, design verification and engineering verification.

1.67 “Product Development Wafer Cost” shall mean the portion of AMD MPU Specific Development Wafer Cost related to Product Development Wafer Starts, determined as the ratio of Product Development Wafer Starts to Development Wafer Starts (for MPU Products).

1.68 “Product Development Wafer Starts” shall mean the Wafer Starts of Product Development Wafers.

1.69 “Production Wafers” shall mean the finished silicon wafers for the Products to be manufactured by the FoundryCo Manufacturing Entities in accordance with the applicable Specifications and using the Qualified Processes, and shall include Risk Starts.

1.70 “Production Wafer Starts” shall mean Wafer Starts for Production Wafers.

1.71 “Qualification Plan” shall mean the qualification tests and schedules to be agreed upon by the parties under which a Qualified Process is established and tested at FoundryCo Manufacturing Entities and relevant Wafers are manufactured using the Qualified Process to meet the Specifications.

1.72 “Qualification” or “Qualified” shall mean the mutual determination that the relevant Wafers meet the Specifications in accordance with the applicable Qualification Plan for a particular Product.

1.73 “Qualified Process” shall mean the wafer manufacturing processes used at FoundryCo for production of relevant Wafers, and any other FoundryCo Manufacturing Entity proprietary wafer manufacturing process approved by the parties to produce relevant Wafers.

1.74 “ Quarterly Business Reviews ” or “ QBRs ” shall mean business reviews held every fiscal quarter by the Partnership Committee or their designees as mutually agreed to by the parties.

1.75 “ Quarterly Technical Reviews ” or “ QTRs ” shall mean technical reviews held every fiscal quarter by the Partnership Committee or their designees as mutually agreed to by the parties.

1.76 “R & D” shall mean research and development.

1.77 “Raw Wafers” shall mean unprocessed or bare silicon wafers purchased by FoundryCo Manufacturing Entities and used by FoundryCo Manufacturing Entities as a substrate to enable the FoundryCo Manufacturing Entities to fabricate Wafers on behalf of AMD as set forth in this Agreement.

1.78 “Raw Wafer Cost” shall mean the actual cost to the FoundryCo Manufacturing Entities of a Raw Wafer.

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

1.79 “Recall” shall mean a recall, field correction, market withdrawal, stock recovery, or other similar action with respect to any Products delivered under this Agreement and related to manufacturing of such Products (and not related to AMD’s Product designs or Specifications) other than Engineering Wafers.

1.80 “Relevant Executive Officer” shall have the meaning set forth in Section 3.2(b).

1.81 “Representatives” shall have the meaning set forth in Section 13.1.

1.82 “Residual Information” shall mean with respect to Confidential Information, information in non-tangible form which may be incidentally retained in the unaided memory of the receiving party’s personnel having had access to the Confidential Information of the disclosing party, and which such personnel cannot identify as Confidential Information of the disclosing party. Such personnel’s memory is “unaided” if the personnel have not intentionally memorized any Confidential Information of the disclosing party.

1.83 “Risk Starts” shall mean Production Wafer Starts for Products that have yet to be accepted by a customer. Process Development Wafers and Product Development Wafers are not Risk Starts.

1.84 “RFQ” shall mean request for quotation with respect to the [****] of [****] as specified in Exhibit B.

1.85 “RMA” shall mean return material authorization. An RMA process is a process by which Products are identified as defective, returned to a FoundryCo Sales Entity or scrapped, and the applicable FoundryCo Sales Entity or FoundryCo Manufacturing Entity undertakes specified remediation activities and provides refunds or credits, as further specified in Exhibit E.

1.86 “RMA Threshold” shall mean a percentage of the Target Yield for each Product, as determined by the Partnership Committee on a Product by Product basis.

1.87 “Sales and Marketing Expenses” shall mean standard sales and marketing expenses, as calculated by FoundryCo in accordance with accounting standards as generally applied by FoundryCo.

1.88 “SOI” shall mean use of a layered silicon-insulator-silicon substrate in the process of manufacturing Wafers.

1.89 “Sort Equipment” shall mean equipment owned as of the Effective Date by FoundryCo to perform Sort Services for MPU Products.

1.90 “Sort Services” shall mean the wafer testing and sorting services to be provided by the applicable FoundryCo Manufacturing Entities upon agreement of the parties to determine conformance of the Wafers with the Specifications.

1.91 “Sort Services Cost” shall mean all cost incurred in providing Sort Services, including the depreciation on Sort Equipment.

1.92 “Specifications” shall mean the AMD Product specifications agreed upon by the parties on a Product by Product basis, initially consistent with AMD’s current specifications for existing Products currently being manufactured by AMD as of the Effective Date.

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

1.93 “Target Yield” shall mean the anticipated Yield for each Product determined on a fiscal quarter basis by the parties as set forth in Section 3.7.

1.94 “[ **** ]” shall mean [****].

1.95 “Transition Period” shall have the meaning set forth in Section 12.3.

1.96 “Transition Services Agreement” shall mean the Transition Services Agreement between AMD and FoundryCo dated of even date herewith.

1.97 “[ **** ]” shall mean [****].

1.98 “Wafers” shall mean Engineering Wafers, Production Wafers, or both, as applicable.

1.99 “Wafer Outs” shall mean completed Wafers processed for delivery to AMD.

1.100 “Wafer Price” shall mean the price of Wafers quoted by FoundryCo Sales Entities to AMD on a Product by Product basis and thereafter set forth on a purchase order from AMD to the FoundryCo Sales Entities.

1.101 “Wafer Starts” shall mean Wafers that have started the manufacturing process.

1.102 “ Warranty Period ” shall mean the time following delivery of a Product when the performance warranty set forth in Section 9.1 is available for such Product. This Warranty Period shall be reviewed and approved by the Partnership Committee on a Product by Product basis, but in the absence of a specific Warranty Period approved by the Partnership Committee, the default Warranty Period for a Product will be [****] months.

1.103 “Yield” shall mean the actual percentage of Die on a Wafer that conform to the Specifications as measured at Wafer sort.

1.104 “Yield Loss” shall mean the percentage of Die on a Wafer that do not conform with the Specifications as measured at Wafer sort.

2. PURCHASE AND CAPACITY COMMITMENTS

2.1 Purchase Commitments.

(a) MPU Products . During the term of this Agreement and subject to Section 2.1(b), AMD agrees to purchase all of AMD’s and the Remaining Discovery Subsidiaries’ MPU Product requirements from FoundryCo Sales Entities in accordance with the terms and conditions of this Agreement, provided that if FoundryCo is not in compliance with its obligations to provide the agreed to capacity or to provide all of the MPU Products pursuant to the Binding Forecasts and applicable purchase orders in a timely manner, within the Yield requirements, on Qualified Processes and in accordance with the Specifications, then the parties agree to meet, discuss and implement a mutually acceptable corrective action plan to address such non-compliance as well as a mutually acceptable plan to allow FoundryCo to provide the agreed to capacity and to provide all of the MPU Products pursuant to the Binding Forecasts and applicable purchase orders in a timely manner, within the Yield requirements, on Qualified Processes and in accordance with the Specifications going forward. Notwithstanding the foregoing, in the event that AMD acquires a business from a third party that either manufactures or has manufactured MPU Products, then AMD shall have a commercially reasonable period of time to transition

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

manufacture of such MPU Products to FoundryCo; provided that such period of time to transition shall not exceed two (2) years from the date of such acquisition, unless consented to by FoundryCo (which consent shall not be unreasonably withheld).

(b) Second Sourcing .

i. Notwithstanding Section 2.1(a), AMD may source up to [****] percent ([****]%) of AMD’s and the Remaining Discovery Subsidiaries’ quarterly MPU Product Wafer requirements with [****] at Process Nodes of [****] nm or greater, until [****] establishes a fabrication facility at an [****] outside [****] with Qualified Processes to manufacture the applicable MPU Products for AMD.

ii. If at any time while AMD may purchase the applicable MPU Products from [****], FoundryCo cannot deliver in a timely manner Qualified Products produced on Qualified Processes that meet the Specifications in accordance with Binding Forecasts, the Partnership Committee shall promptly address the situation, including conducting a prompt review process and implementing a corrective action plan. If, however, such failure to so deliver such Products is causing AMD to fail to meet its material commitments to its customers, and AMD as a result needs to purchase greater MPU Product volumes from [****] than otherwise set forth above, AMD may increase its purchases at [****] for the affected MPU Products above the [****] percent ([****]%) maximum to meet such customer requirements. AMD may thereafter continue to purchase MPU Products over the [****] percent ([****]%) maximum until such time as FoundryCo demonstrates, as mutually agreed upon, that FoundryCo can meet the relevant Specifications and Yields for such MPU Product in a manner reasonably comparable or better than those of [****], as well as meet the applicable supply commitments set forth in this Agreement or as actually required by AMD.

iii. Upon request from AMD and [****], FoundryCo agrees to use commercially reasonable efforts to provide technical assistance to [****] with respect to an agreed upon plan to enable [****]’s efforts to manufacture the applicable MPU Products, including, subject to any applicable third-party sublicensing and disclosure restrictions, granting access and rights to necessary process technology, provided that [****] agrees to use such assistance solely to manufacture applicable MPU Products for AMD and to enter into a confidentiality agreement reasonably satisfactory to FoundryCo. AMD agrees to bear the reasonable expenses approved in advance by AMD and actually incurred by FoundryCo to provide such assistance.

iv. Notwithstanding any of the foregoing, upon the occurrence of [****] Change of Control Transaction, AMD shall not be permitted thereafter to engage [****] as a second source manufacturer of any MPU Products, subject to a reasonable wind-down period to move the production of the applicable MPU Products to Qualified Processes at the FoundryCo Manufacturing Entities without materially affecting AMD’s supply obligations to its customers. FoundryCo agrees, in good faith, to work with AMD to resolve any issues related to AMD’s ongoing customer relationship as a result of AMD’s inability to engage [****] as a second source manufacturer. Notwithstanding the foregoing and except for the reasonable transition period contemplated in the final sentence of Section 2.1(a), to the extent the relevant MPU Products were being made by [****] or [****] at the time AMD acquired the applicable business pursuant to the final sentence of Section 2.1(a), AMD agrees not to second source any MPU Products from [****] or [****] or any company controlled by [****] or [****].

(c) GPU Products.

i. AMD commits to, and the parties agree to work together, to establish FoundryCo’s ability to manufacture GPU Products via a high volume bulk 32 nm process with Specifications to be agreed upon in advance by the parties in writing.

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

ii. At such time as FoundryCo has established a 32 nm Qualified Process, AMD agrees, subject to this Section 2.1(c), that it will purchase from FoundryCo Sales Entities at least [****] percent ([****]%) of AMD’s and the Remaining Discovery Subsidiaries’ monthly Wafer requirements for the GPU Products at all Process Nodes, as further detailed in Exhibit C, ramping up linearly over a five (5) year period beginning with the fiscal month in which the initial [****] percent ([****]%) GPU Product volume sourcing commitment has been met, to at least [****] percent ([****]%) of AMD’s Wafer requirements of its GPU Products (such minimum percentage, the “ GPU Minimum Percentage ”). If for an applicable quarter it is determined that AMD has not placed the GPU Minimum Percentage of AMD’s and the Remaining Discovery Subsidiaries’ GPU Products for manufacture by FoundryCo as set forth herein, the parties agree to meet, discuss and implement a mutually acceptable corrective action plan to address such non-compliance and to enable FoundryCo to manufacture higher volumes of the GPU Products in future.

iii. For each GPU Product (including the first-tape out of such GPU Product), FoundryCo shall have a [****] in accordance with the process set forth in Exhibit B to manufacture such GPU Product. For the avoidance of doubt, the parties agree that FoundryCo shall have such [****] in accordance with the process set forth in Exhibit B with respect to each GPU Product (whether or not such GPU Product is first GPU Product) at each [****] of [****].

iv. AMD agrees not to sell, transfer or otherwise dispose of all or substantially all of its or the Remaining Discovery Subsidiaries’ assets related to GPU Products and related technology (including the equity interests of ATI Technologies ULC or its other subsidiaries that own such assets) to any person (other than to AMD or another Remaining Discovery Subsidiaries) without the consent of FoundryCo, unless the transferee (A) agrees to be bound by the provisions of this Agreement with respect to GPU Products, including FoundryCo’s [****] with respect to each GPU Product and the GPU volume commitment set forth in this section 2.1(c), and (B) agrees to purchase, on an annual basis, GPU Products in an amount equal to the GPU Minimum Percentage (determined at the time of such transfer) of AMD’s volume of total GPU Products purchased from any foundry during the one (1) year period before such transfer, or if such transfer takes place less than one (1) year from the Effective Date, then the annualized volume for the period from the Effective Date to such transfer date.

(d) Embedded Products . FoundryCo shall continue to manufacture the Embedded Products (other than such Products on [****]nm technology), in accordance with the terms of this Agreement, that AMD is manufacturing as of the Effective Date so long as AMD gives FoundryCo commercially viable volumes, as determined by the Partnership Committee.

(e) Other Future Products . AMD shall have no purchase commitment with respect to any Other Future Products; provided, however, that in the event AMD introduces a tape-out of any Other Future Products, FoundryCo shall have a right of first refusal in accordance with the process set forth in Exhibit B to manufacture such Other Future Product (including the first tape-out of such Other Future Product), subject to Qualification of such Other Future Product at such Process Node.

2.2 Capacity Commitment. The parties agree to work in good faith to review the forecast with respect to MPUs provided by AMD pursuant to Section 5.1, including a review of all incremental capital costs and expenditures expected to be incurred by FoundryCo resulting from any increase in the MPU Product volumes pursuant to the MPU Product forecasts. Upon completion of such review, and to the extent agreed to by the parties regarding the implementation of any additional capacity at FoundryCo Manufacturing Entities, FoundryCo shall allocate such additional capacity sufficient to produce the MPU Product volumes indicated in the relevant Binding Forecasts. The parties agree to act in good faith and in reasonable manner in connection

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

with such review and any agreement to allocate such capacity. The parties agree to establish capacity requirements in writing in advance for the manufacture and supply of GPU Products. Notwithstanding the foregoing, FoundryCo will use commercially reasonable efforts to fill any unutilized capacity at FoundryCo Manufacturing Entity facilities that has been allocated to AMD as set forth in this Agreement with production on behalf of third parties, and FoundryCo will offset AMD’s obligations to reimburse FoundryCo’s fixed costs for such unutilized capacity by the percentage of such unutilized capacity FoundryCo uses to manufacture products for third parties; provided that FoundryCo shall not be required to fill such unutilized capacity that has been allocated to AMD if there exists unutilized capacity at FoundryCo Manufacturing Entity facilities that has not been allocated to AMD.

3. PROCESS IMPLEMENTATION

3.1 Operational Coordination. The parties will maintain communication via applicable technical personnel to ensure production and delivery of Products in accordance with the requirements as set forth in this Agreement.

3.2 Partnership Committee .

(a) Partnership Committee Composition . The parties hereto shall create a partnership committee (the “ Partnership Committee ”) which shall have responsibility for the implementation of this Agreement and for the relationship between FoundryCo and AMD. The Partnership Committee shall be comprised of at least four (4) members, with each of AMD and FoundryCo appointing an equal number of representatives. The Partnership Committee will create or approve general guidelines, policies, and procedures governing the process for determining any specific parameters to be mutually established by the parties (e.g., production volume forecast, customer feedback, Specifications, Target Yields). The Partnership Committee will meet (a) on a quarterly basis, (b) at the request of any party in connection with the resolution of a dispute, and (c) at the reasonable request of any party to address significant issues with respect to this Agreement. The Partnership Committee or its designees will also conduct QBRs and QTRs.

(b) Dispute Escalation . If at any point the Partnership Committee members are deadlocked and cannot reach agreement on an issue, the Partnership Committee will notify the relevant executive officer (each, a “ Relevant Executive Officer ”) of AMD and FoundryCo of the issue. If the Relevant Executive Officers reasonably determine that the issue warrants further escalation, the Relevant Executive Officers will then discuss the issue in person or by telephone and the parties shall attempt in good faith to resolve the issue for a period of ten (10) Business Days. If the issue is not resolved, as agreed by AMD and FoundryCo, within such ten (10) Business Day period, the issue will be escalated to the chief executive officers of AMD and FoundryCo.

3.3 New Processes. The parties will discuss in good faith the details of the introduction of new process technologies, technology roadmaps and new Process Nodes at FoundryCo (subject to, in each case, any applicable constraints to which FoundryCo may be subject pursuant to any confidentiality obligations (whether oral or in writing) to or confidentiality agreements with third parties) for use to manufacture Products, including production capacity, ramp time, dependencies and Wafer Prices. As between FoundryCo and AMD, FoundryCo will bear all expenses for introducing new process technology and new Process Nodes, as further described in Exhibit A, other than AMD-Specific Manufacturing Process Technologies.

3.4 New Products. If the parties agree, pursuant to Section 2.1 or otherwise, to add new non-MPU Products for FoundryCo to manufacture on AMD’s behalf, AMD and FoundryCo shall agree in writing in advance on the Specifications, the AMD-Specific Product Qualification Plan and the price for such new non-MPU Products.

3.5 Product Development Wafer Production Run. Upon the agreement of the parties pursuant to a purchase order, FoundryCo will produce Product Development Wafers, using the applicable FoundryCo

 

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.

manufacturing process, and deliver the Product Development Wafers to AMD in accordance with the AMD-Specific Qualification Plan or the Qualification Plan agreed upon by the parties.

3.6 Process Evaluation. AMD shall evaluate the Wafers provided by FoundryCo in accordance with the AMD-Specific Qualification Plan or the Qualification Plan, as applicable. The parties will then assess in accordance with the procedures set forth in Exhibit G whether the applicable manufacturing process fulfills the necessary requirements to manufacture the applicable Products in commercial production quantities in accordance with all applicable Specifications and requirements.

3.7 Yield Calculation Process and Yield Improvements .

(a) Existing Products on Existing Processes . On a fiscal quarter basis within thirty (30) days following the end of the previous fiscal quarter, the parties will meet and review the actual Yields achieved by FoundryCo on a Product by Product basis. The parties will agree in writing on a Product by Product basis for the Target Yields for each Product that will apply to orders placed in the subsequent fiscal quarter. For the first [****] fiscal quarters following the Effective Date, the lot average actual Yields measured over the last completed fiscal quarter prior to the Effective Date for the Products calculated by AMD and provided to FoundryCo shall be used for the Target Yields.

(b) New Products on New Processes . For instances where AMD and FoundryCo have agreed that FoundryCo will manufacture a new Product for AMD and will do so on a new process that has not previously been Qualified to manufacture Products for AMD, the Partnership Committee may set a Target Yield, but Yield and Yield Loss percentages will not be calculated until the parties mutually agree that a sufficient number of Wafers have been produced to generate Target Yield data. The parties will establish in advance mutually-acceptable test criteria for determining conformance of the applicable Die to the applicable Specifications so that the Target Yield data will be determined objectively.

(c) New Products on Existing Processes . For instances where AMD and FoundryCo have agreed that FoundryCo will manufacture a new Product for AMD and will do so on an existing FoundryCo process that has previously been Qualified to manufacture Products for AMD, the Partnership Committee may set a Target Yield, but the Target Yield will not be calculated until the parties mutually agree that a sufficient number of Wafers have been produced to generate Target Yield data, with a presumption that fewer Wafers will need to be produced to calculate such Target Yield data than would be required for new Products on new processes. The parties will establish in advance mutually-acceptable test criteria for determining conformance of the applicable Die to the applicable Specifications so that the Target Yield data will be determined objectively.

(d) Yield Improvements . FoundryCo shall use