Confidential Treatment Requested under 17 C.F.R. §§ 200.80(b)94), 200.83 and 240.24-b-2 Second Amendment and Restatement of ?S? PROCESS DEVELOPMENT AGREEMENT (effective as of December 28, 2002)

Exhibit 10.1

 

Confidential Treatment Requested

under 17 C.F.R. §§ 200.80(b)94),

200.83 and 240.24-b-2

 

Second Amendment and Restatement of

 

“S” PROCESS DEVELOPMENT AGREEMENT

(effective as of December 28, 2002)

 

between

 

INTERNATIONAL BUSINESS MACHINES CORP.

 

And

 

ADVANCED MICRO DEVICES, INC.

 

Confidential treatment has been requested for portions of this exhibit. The copy filed herewith omits the information subject to the confidentiality request. Omissions are designated as *** . A complete version of this exhibit has been filed separately with the Securities and Exchange Commission.

 

 

EXECUTION VERSION

 

This Agreement is made effective as of the 28th day of December, 2002 (hereinafter referred to as the “Effective Date”) by and between International Business Machines Corporation (“IBM”), incorporated under the laws of the State of New York, U.S.A. and having an office for the transaction of business at 2070 Route 52, Hopewell Junction, NY 12533, U.S.A, and Advanced Micro Devices having an office for the transaction of business at One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 “(AMD)”. IBM and AMD may be individually referred to herein as a “Party,” or collectively as the “Parties.”

 

WHEREAS , IBM has been developing leading edge semiconductor manufacturing processes with Sony and Toshiba, and the Parties hereto desire to continue to participate in development efforts under this Agreement;

 

WHEREAS , the Parties possess complementary skills and know-how, which the Parties wish to contribute toward such process development;

 

WHEREAS , each Party agrees to provide certain personnel and grant the other Parties certain technology licenses in support of such process development;

 

WHEREAS , through the use of such complementary skills and know-how the Parties desire to achieve resource efficiencies and cost savings, and reduce the technical risk associated with the development of high end semiconductor processes in order to complete development of and put into production, leading edge high end semiconductor manufacturing processes sooner than would be possible with any of the Parties acting independently;

 

NOW THEREFORE , in consideration of the premises and mutual covenants contained herein, as well as for other good and valuable consideration, the receipt and sufficiency of which is hereby acknowledged, the Parties agree as follows. For avoidance of doubt, the Agreement as defined below covers its subject matter after its Effective Date including matters provided for in the “S” Process Development Agreement (Effective as of December 28, 2002) as amended and restated on September 15, 2004 and as set forth herein.

 

SECTION 1 - DEFINITIONS

 

Unless expressly defined and used with an initial capital letter in this Agreement, words shall have their normally accepted meanings. The headings contained in this Agreement or in any exhibit, attachment or appendix hereto are for reference purposes only and shall not affect in any way the meaning or interpretation of this Agreement. The word “shall” is mandatory, the word “may” is permissive, the word “or” is not exclusive, the words “includes” and “including” are not limiting, and the singular includes the plural. The following terms shall have the described meanings:

 

“Agreement” means the terms and conditions of this Second Amendment and Restatement of “S” Process Development Agreement together with any exhibits, attachments and appendices hereto.

 

“AMD Bump Project Leader” means the individual, if any, appointed by AMD pursuant to Section 4.4 below.

 

“AMD Project Leader” means the individual, if any, appointed by AMD pursuant to Section 4.5 below.

 

“AMD FMV” means a single AMD flash memory venture at any point in time, in which AMD has an ownership interest representing a right to participate in making decisions for such flash memory venture (i.e. a shareholder’s right to vote), which is the lesser of (i)  *** percent ( *** %) or (ii) the largest single owner, but not less than *** percent ( *** %) of such flash memory venture, and which produces flash memory products, provided, that such entity shall be considered an AMD FMV only so long as such ownership exists.

 

“AMD High Performance Integrated Circuit” means an Integrated Circuit manufactured using an AMD High Performance Process.

 

“AMD High Performance Process” means any 32nm, 22nm or subsequent node CMOS semiconductor manufacturing process which incorporates portions of High Performance Device Information, which AMD uses exclusively to produce the highest performing *** percent ( *** %) of wafers manufactured in the applicable technology generation (e.g. 32nm, 22nm) in any given quarter. Performance will be determined by AMD’s AC and DC transistor performance data, wherein any disputes will be resolved by the Management Committee.

 

“AMD Non-High Performance Integrated Circuit” means an Integrated Circuit manufactured using an AMD Non-High Performance Process.

 

“AMD Non-High Performance Process” means AMD’s 32nm, 22nm or subsequent node CMOS semiconductor manufacturing processes used by AMD to manufacture Semiconductor Products other than AMD High Performance Integrated Circuits.

 

“AMD Pre-T0 Project Leader” means the individual, if any, appointed by AMD pursuant to Section 4.3 below.

 

“AMD Pre-T0 Steering Committee Member” means the individual appointed by AMD pursuant to Section 4.2 below, to provide technical guidance to the Management Committee for the Pre-T0 Activities.

 

“ASIC Product” shall mean an SOI Integrated Circuit or AMD High Performance Integrated Circuit that is not a Foundry Product and wherein all of the following conditions are met: (i) at least one of (a) the functional requirements, or (b) the design, for such SOI Integrated Circuit or

 

***	Confidential Treatment Requested

 

AMD High Performance Integrated Circuit product is provided to a Party from a Third Party; (ii) such Party participated in an aspect of the definition and design of such product; and (iii) such Party is contractually bound to manufacture such product solely for, and to sell such product solely to, such Third Party or its distributor or other recipient solely for the benefit of such Third Party, provided that ASIC products shall not include SOI Integrated Circuits or AMD High Performance Integrated Circuits in which the Party modifies its product designs to add or modify a feature or function required by the Third Party, such modifications comprising a change of less than *** percent ( *** %) of the logical functions of the product, even if said product design is only made available to the Third Party.

 

“Background Know-How” means methods, techniques, designs, structures, software, and specifications developed or acquired by a Party outside the performance of the Process Development Projects, which such Party provides to the other Party for use in a Process Development Project pursuant to Section 3. Such Background Know-How shall not include, Packaging Technology, Mask Fabrication and Photoresist Technology, Memory, SiGe Technology, Chip Designs or Post-Silicon Devices.

 

“BEOL” (Back End of Line) shall mean those aspects of Background Know-How and Specific Results that are directed to methods and processes of interconnecting the source, gate, or drain electrodes of FET transistors formed on a wafer, including initial passivation of such FET transistors with a dielectric, up to and including polyimide passivation and final via formation but not including Bump Technology and Packaging Technology. For the avoidance of doubt, “BEOL” shall not include local interconnects made of tungsten.

 

“Bulk CMOS” means 90nm, 65nm and 45nm CMOS semiconductor manufacturing technology carried out on a wafer that is not an SOI Wafer.

 

“Bulk CMOS Information” means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, and/or (ii) selected by IBM either for incorporation into an IBM Bulk CMOS process or otherwise pursuant to Section 3.4.

 

“Bump Technology” means the technology associated with connecting an Integrated Circuit to a chip carrier including IBM’s collapsible chip carrier connection (“C4”) interconnect technology as further defined in Exhibit A that is developed during the term if this Agreement for use with, but not limited to, the semiconductor process technologies also developed under this Agreement. Bump Technology shall include the following process steps: bump limiting metallurgy deposition, photolithography, solder deposition, etching, solder reflow and cleaning, and non-solder interconnect technology.

 

“ *** ”

shall mean *** and its subsidiaries located in *** .

 

“ *** -AMD Manufacturing Facility” shall mean any facility for the manufacture of Integrated Circuits located in *** or Dresden, Germany and either owned entirely by *** and AMD or owned by *** , AMD and all of the remaining such ownership interest is solely owned or

 

***	Confidential Treatment Requested

 

controlled, directly or indirectly, by a government entity or one or more corporations, companies or other entities which are purely financial investors who are not engaged in the design, development, manufacture, marketing or sale of Semiconductor Products.

 

“Chip Design(s)” means any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that “Chip Designs” shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM macro cells) as well as such test chips themselves used for the development work of the Process Development Projects unless specifically excluded (for the avoidance of doubt, this phrase means that such structures or macros that are specifically designated as owner proprietary shall not be considered Specific Results), (iii) other product designs as mutually agreed by the Parties to be used as qualification vehicles in the Process Development Projects, or (iv) ESD protection devices as used in the Project Test Sites and ESD groundrules and models as defined in the Design Manual. For the avoidance of doubt, all of (i) through (iv) above shall be treated as Specific Results to the extent utilized in a Process Development Project.

 

“CMOS 10S” means a 90 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit A.1, attached hereto.

 

“CMOS 10SE” means a 90 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 10S, as further defined in Exhibit A.2.

 

“CMOS 11S” means a 65 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit A.3.

 

“CMOS 11S2” means a 65 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 11S, as further defined in Exhibit A.4.

 

“CMOS 12S” means a 45 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, for the fabrication of SOI Integrated Circuits, as further defined in Exhibit A.5.

 

“CMOS 12S2” means a 45 nanometer CMOS logic fabrication process currently under development by IBM, the development of which is to be continued pursuant to this Agreement, which is a performance enhanced version of CMOS 12S, as further defined in Exhibit A.6.

 

“CMOS 13S” means a 32 nanometer CMOS logic fabrication process researched and evaluated for feasibility in the Pre-T0 Activities and/or thereafter further developed, all pursuant to this Agreement to be further defined in Exhibit A.7.

 

“CMOS 13S2” means a 32 nanometer CMOS logic fabrication process, which is a performance enhanced version of CMOS13S, and which is researched and evaluated for feasibility in the Pre-T0 Activities and/or thereafter further developed, all pursuant to this Agreement to be further defined in Exhibit A.8.

 

“CMOS 14S” means a 22 nanometer CMOS logic fabrication process researched and evaluated for feasibility in the Pre-T0 Activities and/or thereafter further developed, all pursuant to this Agreement to be further defined in Exhibit A.9.

 

“Designated Invention” means an Invention for which a patent application has been filed by one or more of the Parties pursuant to Sections 11.1 or 11.2.

 

“Derivative Process(es)” shall have the meaning ascribed to it in Section 8.1

 

“Development Facilities” means the (i) IBM Development Facilities and (ii) any other facilities agreed to by the Parties in writing.

 

“Embedded DRAM” or “eDRAM” means a device that either (i) primarily carries out logic functions, and includes one or more dynamic random access memory (DRAM) cells embedded within logic circuitry on the same semiconductor substrate, or (ii) primarily carries out memory functions, and includes one or more DRAM cells in combination with a static random access memory (SRAM) array on the same semiconductor substrate (including an array of SRAM cells linked with bit lines, word lines, sense amplifiers and decoders).

 

“Foundry Company(ies)” means an entity having a majority of its revenue arising from the sale of Integrated Circuits wherein all the following conditions are met: (i) the *** , or *** and/or *** , for such Integrated Circuit product are *** ; (ii)  *** ; and (iii)  *** is contractually bound to *** . Foundry Company also includes any other entity that has as its *** , wherein at least *** percent ( *** %) of the ownership interest in such entity is held by a *** (as defined in the first sentence of this paragraph), and wherein such *** .

 

“Foundry Product” shall mean an Integrated Circuit wherein all the following conditions are met: (i) the *** , or *** and/or *** , for such Integrated Circuit product *** ; (ii)  *** of such product (except for providing standard design libraries, design enablement tools or other intellectual property to the Third Party to specifically assist with the design of the product); and (iii)  *** is contractually bound to *** .

 

“High Performance Device Information” means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created on substrates, not including *** or *** .

 

***	Confidential Treatment Requested

 

“High Performance Integrated Circuit” means an Integrated Circuit manufactured in a 32nm, 22nm or subsequent node CMOS semiconductor manufacturing process using High Performance Device Information.

 

“High Sensitivity Pre-T0 Information” shall have the meaning ascribed to it in Section 8.18.

 

“IBM Bump Technology Project Leader” means the individual appointed by IBM pursuant to section 4.4 below.

 

“IBM Development Facilities” means the (i) IBM 200mm or 300mm wafer process development facility used for conducting the Process Development Projects; (ii) the IBM Thomas J. Watson Research Center: and (iii) any other IBM facilities agreed to by the Parties in writing.

 

“IBM Pre-T0 Activities” means the activities conducted by IBM on the CMOS 13S, CMOS 13S2 and CMOS 14S logic fabrication processes researched and evaluated for feasibility by IBM prior to the Commencement Date.

 

“IBM Pre-T0 Information” means all information and items developed or acquired by IBM pursuant to the IBM Pre-T0 Activities and delivered by IBM, in its sole discretion, to the Pre-T0 Activities.

 

“IBM Pre-T0 Project Leader” means the individual appointed by IBM pursuant to Section 4.3, below, to provide day-to-day oversight for the Pre-T0 Activities.

 

“IBM Project Leader” means the individual appointed by IBM pursuant to Section 4.5, below, to provide day-to-day oversight for the Process Development Projects.

 

“IBM Pre-T0 Steering Committee Member” means the individual appointed by IBM pursuant to Section 4.2, below, to provide technical guidance to the Management Committee for the Pre-T0 Activities.

 

“Industry Standard CMOS” means a 32nm, 22nm or subsequent node CMOS semiconductor manufacturing process for high volume foundry manufacturing of Semiconductor Products ( *** ) whose price and performance characteristics are similar to *** .

 

“Industry Standard Information” means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, or (ii) applicable to Industry Standard CMOS and selected by IBM either for incorporation into an IBM Industry Standard CMOS process or otherwise selected pursuant to Section 3.4.

 

***	Confidential Treatment Requested

 

“Integrated Circuit” means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, “Integrated Circuit” shall include charge-coupled devices (“CCDs”).

 

“Invention” means any invention, discovery, design or improvement, conceived or first actually reduced to practice solely or jointly by one or more Representatives of one or more of the Parties or their respective contractors during the term of this Agreement and in the performance of the Process Development Projects.

 

“Licensed Product” means Integrated Circuits that include Bulk CMOS Information, Industry Standard Information, High Performance Device Information, SOI Device Information, or any combination thereof, other than Foundry Products.

 

“Lithography” shall mean those aspects of Background Know-How and Specific Results directed to (a) process technology-dependent ground rules or process technology-dependent special rules for shapes replication as developed by the Parties for the generation of photomasks used for development and qualification of a semiconductor process technology in the Process Development Projects, (b) resolution enhancement techniques specifically created pursuant to the Process Development Projects to generate mask build data, (c) such photomasks themselves and the data files used therefor as are used in the Process Development Projects, (d) lithography process sequence as utilized in the Process Development Projects, and (e) mask data generation sequence as utilized in the Process Development Projects.

 

“Management Committee” shall have the meaning ascribed to it in Section 4.1.

 

“Mask Fabrication and Photoresist Technology” shall mean any process, procedure, Proprietary Tools (e.g. the Niagara software developed by IBM), or hardware tool used in the fabrication of photomasks, as well as the photomasks themselves, and/or the formulation and/or manufacture of photoresist; provided, however, that “Mask Fabrication and Photoresist Technology” shall not include Lithography or the evaluation of photomasks or photoresists for use in the technologies developed and researched hereunder.

 

“Memory” means Chip Designs and fabrication processes specifically related to read only memory (ROM), dynamic random access memory (DRAM), programmable ROMs, magnetic RAM (MRAM), ferroelectric RAM, and Embedded DRAM. For the avoidance of doubt, “Memory” shall not include static RAM (SRAM) macros utilized in the Process Development Projects as test vehicles.

 

“Net Selling Price” for each unit of a particular ASIC Product or wafers (only pursuant to Section 5.7) means the net revenue recorded by AMD (including Wholly Owned Subsidiaries and Related Subsidiaries of AMD) with respect to an ASIC Product or such wafers (only pursuant to Section 5.7) less (a) shipping, (b) insurance, and (c) sales, value added, use or excise taxes, to the extent to which they are actually paid or allowed, and less allowances to the extent they are actually allowed. If ASIC Products or such wafers (only pursuant to Section 5.7) are

 

sold, leased or otherwise transferred in a higher level of assembly or in the course of a transaction that includes other products or services with no separate bona fide price to be charged for the ASIC Products, the applicable Net Selling Price for the purpose of calculating royalties shall be the fair market value of the ASIC Product or such wafers (only pursuant to Section 5.7), but no less than the average Net Selling Price of all such units of other ASIC Products or such wafers (only pursuant to Section 5.7) sold, leased, or otherwise transferred to a Third Party by AMD (and/or by Wholly Owned Subsidiaries and Related Subsidiaries of AMD), whichever the case may be, during the preceding half year.

 

“Packaging Technology” means any process, procedure, software, or hardware tools used in the packaging of integrated circuit products into single-chip packages, multi-chip packages, or any other higher levels of assembly,; provided, however “Packaging Technology” shall not include the formation of layers on a wafer up to and including the final via layer (referred to as LV, TV, or FV level) and shall not include Bump Technology, but shall include any process, procedure, or practice subsequent to any such steps included in Bump Technology.

 

“Post-Silicon Devices” means transistors on substrates other than silicon or transistors with critical dimensions less than *** nm which are not *** or *** , unless otherwise set forth in this Agreement (e.g. Exhibit A.10, which may be updated from time to time by the Parties).

 

“Pre-T0 Activities” means the IBM Pre-T0 Activities and the activities conducted on the CMOS 13S, CMOS 13S2 and CMOS 14S logic fabrication processes researched and evaluated for feasibility under this Agreement pursuant to the technical objectives, and the Pre-T0 In-Scope Technical Subjects, as further defined in Exhibit A and the schedule set forth in Exhibit B.

 

“Pre-T0 Exit” means the point in time where development work begins on the Process Development Project. At this point in the program the Management Committee has determined the Strategic Technology Objectives, Technology Implementation Options and the T-Bulk, T1 and T2 dates for the applicable technology.

 

“Pre-T0 In-Scope Technical Subjects” means the subjects listed in Exhibit A.10, as updated from time to time by agreement of the Management Committee.

 

“Pre-T0 Information” means the IBM Pre-T0 Information and all information and items developed or acquired pursuant to the Pre-T0 Activities.

 

“Pre-T0 Steering Committee” shall have the meaning ascribed in Section 4.2.

 

“Process Development Project(s)” means the CMOS 10S, CMOS 10SE, CMOS 11S, CMOS 11S2, CMOS 12S, CMOS 12S2, CMOS 13S , CMOS 13S2 and if its development is continued pursuant to this Agreement, CMOS14S, development work and any Bump Technology development work conducted jointly by Representatives of the Parties pursuant to the terms and conditions of this Agreement, as more fully set forth in Section 3.1, below.

 

***	Confidential Treatment Requested

 

“Project Leaders” means the IBM Project Leader and the AMD Project Leader.

 

“Proprietary Tools” means software (in source code form or in object code form), models and/or data, and other instrumentalities that are not commercially available and are either owned by a Party or under which a Party has the right to grant royalty-free licenses, and that are used in Process Development Projects.

 

“Qualification” means the T2 date identified in the schedule for each Process Development Project, as set forth in Exhibit B.

 

“Related Subsidiary” shall mean a corporation, company or other entity:

 

(a)

one hundred percent (100%) of whose outstanding shares or securities (such shares or securities representing the right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by the Parties hereto; or

 

(b)

which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity one hundred percent (100%) of whose ownership interest representing the right to (i) make the decisions for such corporation, company or other entity, or (ii) vote for, designate, or otherwise select members of the highest governing decision making body, managing body or authority for such partnership, joint venture, unincorporated association or other entity is, now or hereafter, owned or controlled, directly or indirectly, by the Parties hereto;

 

provided that in either case, such entity shall be considered a Related Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to the Related Subsidiary, only so long as such ownership or control exists.

 

“Representative(s)” means, a Party’s employees and employees of a Party’s Wholly Owned Subsidiaries.

 

“Semiconductor Product” means a component that contains an Integrated Circuit on a single or multichip module that incorporates a means of connecting those Integrated Circuits with other electronic elements (active or passive) and/or means to make external electrical connections to such elements, but which excludes any means for a user to operate the functions therein (e.g., buttons, switches, sensors).

 

“Server” means an electronic device performing information processing functions that primarily provides shared applications, resources, information, or services to other systems or collections of systems or multiple end-users/clients through an internal or external communications connection or network, or through the Internet and is designed to support either AIX or another UNIX operating system.

 

“Silicon-Germanium Technology” or “SiGe Technology” means semiconductor fabrication processes and design techniques incorporating silicon and germanium layers, including those processes and design techniques for use in HEMTs, photodetectors, HBTs or any other applications of bipolar transistors, provided, however, “SiGe Technology” shall not include strained silicon channel MOSFET or any mobility enhancement techniques for FETs techniques carried out on SOI Wafers or High Performance Integrated Circuit wafers. Furthermore, “SiGe Technology” shall not include material and device learning out of “SiGe Technology” that is applicable to the items outlined in Exhibit A.10 of this Agreement under the “FEOL” section of Pre-T0 In-Scope Technical Subjects.

 

“Silicon-On-Insulator Wafer” or “SOI Wafer” shall mean a, single-crystal silicon wafer bearing a horizontally-disposed isolating silicon dioxide (SiO ₂ ) layer, in turn bearing a single-crystal silicon layer or a polysilicon layer, which is separated from the underlying silicon by the silicon dioxide layer and in which one or more active or passive integrated circuit structures are formed.

 

“SOI Device Information” means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created on commercially available SOI Wafers other than Bulk CMOS or Industry Standard Information.

 

“SOI Integrated Circuit” shall mean an Integrated Circuit fabricated utilizing SOI Device Information and built on SOI Wafers.

 

“Specific Results” shall mean information and items, other than i) Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Memory, v) SiGe Technology, vi) Chip Designs, and vii) Post-Silicon Devices, developed and/or contributed to the Process Development Projects by the Parties pursuant to the development work of the Process Development Projects as follows:

 

The documentation produced for the Process Development Projects as set forth in Exhibit J attached hereto (“Documentation”);

 

All information and items resulting from the Process Development Projects and results of the Pre-T0 Activities selected by the Management Committee for inclusion in the CMOS 13S, CMOS 13S2 or CMOS 14S process, including but not limited to methods, techniques, unit processes, process flows, structures in silicon, test software, and specifications for equipment, chemicals, masks and consumables;

 

Any Background Know-How provided to the Process Development Project(s) by a Party pursuant to Section 3, below.

 

“Subsidiary” means a corporation, company or other entity:

 

(a)

more than fifty percent (50%) of whose outstanding shares or securities (representing the right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by a Party hereto, or

 

(b)

which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, but more than fifty percent (50%) of whose ownership interest representing the right to make the decisions for such corporation, company or other entity is now or hereafter, owned or controlled, directly or indirectly, by a Party hereto,

 

provided that in either case such entity shall be considered a Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to Subsidiaries, only so long as such ownership or control exists.

 

“Technical Coordinators” means the individuals referred to in Section 4.7, below.

 

“Term” means the period of time from the Effective Date and ending in accordance with the terms of Section 12.1.

 

“Test Site” means a device or circuit evaluation site on a wafer.

 

“Third Party” or “Third Parties” means an entity or entities other than the Parties or their Wholly Owned Subsidiaries or Related Subsidiaries.

 

“Wholly Owned Subsidiary” shall mean 1) a corporation, company or other entity:

 

(a) one hundred percent (100%) of whose outstanding shares or securities (such shares or securities representing the right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by a Party; or

 

(b) which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity but one hundred percent of whose ownership interest representing the right to (i) make the decisions for such corporation, company or other entity, or (ii) vote for, designate, or otherwise select members of the highest governing decision making body, managing body or authority for such partnership, joint venture, unincorporated association or other entity is, now or hereafter, owned or controlled, directly or indirectly, by a Party;

 

provided that in either case such entity shall be considered a Wholly Owned Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to Wholly Owned Subsidiaries, only so long as such ownership or control exists; or 2) a corporation, company or other entity:

 

(c) at least seventy five percent (75%) of whose outstanding shares or securities (such shares or securities representing the right to vote for the election of directors or other managing authority) are, now or hereafter, owned or controlled, directly or indirectly, by a Party; or

 

(d) which does not have outstanding shares or securities, as may be the case in a partnership, joint venture or unincorporated association, or other entity but at least seventy five percent (75%) of whose ownership interest representing the right to (i) make the decisions for such corporation, company or other entity, or (ii) vote for, designate, or otherwise select members of the highest governing decision making body, managing body or authority for such partnership, joint venture, unincorporated association or other entity is, now or hereafter, owned or controlled, directly or indirectly, by a Party

 

provided, that in either case (c) or (d) above, (i) all of the remaining such ownership interest is solely owned or controlled, directly or indirectly, by one or more corporations, companies or other entities which are purely financial investors who are not engaged in the design, development, manufacture, marketing or sale of Semiconductor Products, and (ii) such entity shall be considered a Wholly Owned Subsidiary, and shall be entitled to retain the licenses and other benefits provided by this Agreement to Wholly Owned Subsidiaries, only so long as such ownership or control exists.

 

SECTION 2 – IBM Development Facilities

 

2.1	IBM has established the IBM Development Facilities, wherein its 200mm and 300mm wafer process development facility used for conducting the Process Development Projects is located in East Fishkill, New York.

 

2.2

IBM shall be responsible for the operations of the IBM Development Facilities, including, but not limited to capacity, staffing, and capital purchases. Process Development Projects shall be conducted primarily at the IBM Development Facilities and the Parties agree that the development work performed under this Agreement after Pre-T0 Exit will be conducted primarily in IBM’s 300mm East Fishkill Facility. In addition to the IBM Development Facilities, IBM may utilize other facilities to conduct elements of the development work associated with the Process Development Projects. In addition, the Parties may mutually agree to utilize AMD development facilities for specifically defined elements of the Process Development Projects. If the Management Committee members so agree, such agreement shall be documented in writing and signed by the Parties.

 

2.3

Should IBM desire, at its own discretion, that the Process Development Projects performed under this Agreement after Pre-T0 Exit be primarily conducted at facilities other than IBM’s 300mm East Fishkill facility, it shall provide notice of such desire to AMD no later than one (1) year prior to the intended change. The Parties will meet to

 

discuss and attempt to agree on such a move. If the Parties are unable to reach agreement, the Management Committee shall negotiate a mutually agreeable reasonable wind down plan to terminate (for convenience and without liability to either Party) the development relationship set forth in this Agreement. In the event of such termination, AMD shall be entitled to immediately exercise its rights in accordance with Section 8.9 below, with payment under Section 5.8.a or Section 5.8.b, as mutually agreed upon by the Parties at that time.

 

SECTION 3 - SCOPE OF PROCESS DEVELOPMENT PROJECTS/OTHER PROJECTS

 

3.1

The Parties agree to jointly develop semiconductor manufacturing process technology based on IBM’s “S” high performance technology roadmap on commercially available wafers that meet the requirements set forth as “Strategic Technology Objectives” in Exhibit A (hereinafter referred to as “Strategic Technology Objectives”) in accordance with the schedule set forth in Exhibit B (hereinafter referred to as “Development Schedule”). The Parties agree that the process technology so developed, shall be high performance, leading edge technology and, to the extent consistent with the Strategic Technology Objectives, shall be cost efficient. Any modification to such Strategic Technology Objectives or Development Schedule requires the mutual agreement of the Parties. For the avoidance of doubt, none of the Process Development Projects shall include the development of i) Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Memory, v) SiGe Technology, vi) Chip Designs, or vii) Post-Silicon Devices.

 

3.2

The Parties agree that Exhibit A also sets forth the Pre-T0 In-Scope Technical Subjects and the potential technology implementation options for each Process Development Project. The Parties shall work together to evaluate the various options available, including individual process module feasibility, integration, characterization and qualification. The goal of such evaluation is to agree on an integrated process technology that meets the Strategic Technology Objectives. If the Project Leaders are unable to agree on a particular process module to be developed, or should they disagree as to the continued development of a process module that was previously selected, the process module preferred by IBM shall be pursued in the applicable Process Development Project.

 

3.3

For information other than that developed by the Parties in a given Process Development Project to be considered Specific Results for that Project, including Background Know-How, it must be either deliberately provided to the Process Development Projects by the owner of such information, or be evaluated by the Project Leaders, pursuant to Section 3.2, for possible use in a Process Development Project . In the event such item of information is provided, and the Party owning such information notifies the Project Leaders within thirty (30) days after such owning Party’s disclosure or the initiation of

 

such evaluation that such information should be withdrawn, such owning Party may withdraw such information from use in the Process Development Projects and all such information in tangible form associated therewith shall be returned to such owning Party and such tangible information shall not become Specific Results. In the event of such withdrawal, any non-tangible information related to such information retained in the minds of the non-owning Party’s employees shall be treated as Specific Results by the non-owning Parties. Absent such notice and withdrawal within thirty (30) days, all information deliberately provided by the owner of such information or evaluated by the Project Leaders shall be treated as Specific Results.

 

3.3.1

Any issue as to whether information was deliberately provided to the Process Development Projects shall be resolved by the Project Leaders based on either of the following criteria:

 

3.3.1.1

whether the information was deliberately exposed to the other Parties by a Representative of the owner of such information; or

 

3.3.1.2

whether the evaluation of the information by the Representatives was validly considered for incorporation into the Process Development Projects.

 

If the Project Leaders cannot agree, such issue shall be resolved by the Management Committee in accordance with the criteria in Sections 3.3.1.1 and 3.3.1.2.

 

3.3.2

Each Party shall be responsible for instructing its Representatives on methods of proper introduction of information into the Process Development Projects, and the consequences under Section 7.10, below, of information that is inadvertently obtained.

 

3.4

During a given Process Development Project, the IBM Project Leader shall designate elements of the Specific Results and Background Know-How thereof that IBM will be applying toward development of its applicable Bulk CMOS or its applicable Industry Standard CMOS process. IBM shall provide an initial designation of such elements at the completion of its initial feasibility studies for the applicable Process Development Project (set forth in Exhibit B as the “T-Bulk date”), and IBM shall provide a final designation of such elements no later than the “T1” date for the applicable Process Development Project, as set forth in Exhibit B. AMD agrees that IBM reserves the right to change such designations between its initial designation and its final designation. In either case, prior to making such determinations IBM shall consult with AMD, who shall provide its input as to the applicability of such elements to a Bulk CMOS or Industry Standard CMOS process; provided, however, that IBM shall have the right to make any and all final decisions as to designation and application of such elements to its Bulk CMOS or its Industry Standard CMOS process. The Project Leaders shall agree upon a specific process by which IBM will make this designation and by which IBM will

 

address any requests for clarification by AMD within reasonable time periods. For the avoidance of doubt, in addition to Specific Results designated as Bulk CMOS Information or Industry Standard Information as described in this section 3.4, Bulk CMOS Information and Industry Standard Information shall include those items listed in Exhibit K attached hereto. Exhibit K may be updated from time to time by written mutual agreement of the Management Coordinators.

 

3.5

Each Party shall have access to all Specific Results and shall be solely responsible, including the cost therefor, for the transfer of Specific Results to its own facilities. In addition to Representatives, AMD may assign additional personnel to IBM facilities to assist with such transfer. The number of additional personnel and the duration of their assignment shall be mutually agreed to by the Management Committee. As part of each Process Development Project, the Project Leaders shall coordinate the completion of the Documentation for such Process Development Project and each Party shall have access to all such Documentation. Notwithstanding the foregoing, subsequent to the Parties establishing the Strategic Technology Objectives (at Pre-T0 Exit ) for CMOS14S, only a subset of the Documentation shall be prepared for the CMOS 14S Process Development Project, as determined by the Project Leaders. Should AMD have any questions regarding the Documentation as they are transferring such Specific Results to their own facilities, IBM agrees to provide reasonable telephonic, videoconference or email support through its Technical Coordinator to address such questions during normal business hours. Each Party shall be solely responsible for obtaining any and all regulatory approvals as may be required to utilize Specific Results at its facilities, and shall be solely responsible for the cost of equipment and consumables as may be required to utilize the Specific Results at its facilities.

 

3.6

Without liability to the other Parties for breach hereof, to the extent known by a Party disclosing information for use in any Process Development Project, prior to such disclosure, such disclosing Party agrees to promptly notify the other Parties of any limitations on the uses of such information, whether such use would violate or whether such information is protected by any copyright or mask work or similar right of any Third Party. Upon such notification, the Parties may agree to accept such information into the Process Development Project subject to such limitations. Upon the failure to make such notification, or if any such limitation arises after disclosure by the disclosing Party, then the Parties shall attempt to work together to find a mutually agreeable solution. Each Party further agrees to use reasonable efforts to ensure that it will not design or develop the Process Development Projects in such a way that requires the use of any Third Party confidential information, which is not available to the other Parties for their use as aforesaid. Each Party further agrees to use reasonable efforts to ensure that it will not disclose to the other Parties any information considered confidential by it or by any Third Party which information does not relate to the Process Development Projects.

 

3.7	To the extent that either Party enters into a development agreement with its equipment and materials suppliers and elects to disclose the results of any such development to the

 

other Party as Background Know-How under a Process Development Project or Pre-T0 Activity, and to the extent the disclosing Party has the right to do so, the disclosing Party agrees to notify the other Party of such development agreement. Furthermore, the disclosing Party will consent to include a reasonable number of Representatives of the other Party in technical discussions with each such supplier. The Parties will use reasonable efforts to accommodate such technical discussions at either Party’s facilities or via teleconference. Any additional information generated at such meetings shall be the Background Know-How of the Party who has entered into such development agreement.

 

3.8	Bump Technology.

 

3.8.1

The Parties agree that all terms and conditions of the “C-4 Agreements” shall continue in full force and effect, and shall not be superseded by this Agreement. For purposes of this Agreement, the “C-4 Agreements” shall mean collectively (1) the C-4 Plating Technology Transfer and Licensing Agreement between AMD and IBM having a last signature date of April 29, 1999; (2) the C-4 Tighter Pitch Workshop Agreement between AMD and IBM having a last signature date of March 23, 2001; (3) the C-4 Technical Assistance and Short Loop Support Agreement between AMD and IBM having a last signature date of July 16, 2001; and (4) the Letter Agreement having a signature date of September 13, 2004.

 

3.8.2

The Parties agree that if IBM, in its sole discretion, continues to develop Bump Technology any time after *** and during the remainder of the Term of this Agreement, the Parties have established Bump Technology Process Development Projects in this Agreement and may establish new Bump Technology Process Development Project(s) in signed amendment(s) to this Agreement. In either case, IBM agrees that AMD will not be required to pay any additional fees to IBM for access to and a license to said technology. If a separate Bump Technology development agreement is entered between IBM and any Third Party(ies), IBM will use reasonable efforts to include AMD in such development efforts, subject to the negotiation of mutually agreeable terms and conditions between AMD and the participants in such development efforts.

 

a.

If Bump Technology is established as a Process Development Project under this Section 3.8.2: (i) the Parties agree that AMD may exercise at least the same rights to use and implement and have the same obligations with regard to said Bump Technology as AMD currently exercises and has under the C-4 Agreements and (ii) if the Parties, thereafter, mutually agree to expand the scope of a Bump Technology Process Development Project, such expansion will be governed by the terms and conditions of Section 14.

 

3.8.3

If Bump Technology is established as a Process Development Project, the Parties will provide, to the extent a Party has the right to do so without the payment of additional compensation to any Third Party, to the Bump Technology Process

 

***	Confidential Treatment Requested

 

Development Project any relevant information as Background Know-How. Additionally, to the extent that IBM does enter a separate Bump Technology development agreement with a Third Party and IBM has the right to do so without the payment of additional compensation to any Third Party, IBM will grant a sublicense to AMD to the technology developed thereunder without requiring any additional fees, which sublicense shall be consistent with the licenses granted to AMD under this Agreement and the C-4 Agreements.

 

SECTION 4 - MANAGEMENT AND STAFFING OF THE PROCESS DEVELOPMENT PROJECTS

 

4.1	The Parties hereby create a Management Committee, with equal representation from each Party. The responsibilities of the Management Committee are set forth in Exhibit D, attached hereto. All decisions of the Management Committee shall be by mutual consent.

 

The Management Committee is comprised initially of the following individuals:

 

 

Either Party may change its member of the Management Committee by written notice to the other Party. The Management Committee will conduct regular meetings on dates and at locations determined by the Management Committee. Meetings of the Management Committee may be held in person, by teleconference or by videoconference.

 

4.1.1

The Management Committee shall establish a regular review process with the appropriate senior business executives of each of the Parties of at least the level of Vice President or other comparable level. Such review shall include review of an overall progress report to be prepared by the Project Leaders. The responsibilities of the Management Committee are set forth in Exhibit D. In addition, the

 

***	Confidential Treatment Requested

 

Management Committee shall establish a Pre-T0 Steering Committee to oversee the Pre-T0 Activities.

 

4.1.2

Should either Party reasonably determine that the process technology to be developed under the Process Development Projects is no longer meeting the Strategic Technology Objectives or the Development Schedule, or brings forth empirical evidence of changes in the competitive marketplace for semiconductor technology such that the Strategic Technology Objectives and/or the Development Schedule are no longer competitive, or if the Parties cannot agree upon the Strategic Technology Objectives or Development Schedule for CMOS 13S or CMOS13S2 prior to Pre-T0 Exit, such Party may present such problem to the Management Committee for discussion. If the Management Committee, after the exercise of reasonable efforts in the conduct of such discussions, fails to reach mutual agreement as to a resolution of such Party’s concerns then any Party may refer such concerns to the senior executives described in Section 4.1.1, above, which senior executives shall discuss and meet in person, if necessary, in order to attempt to resolve such Party’s concerns. If such senior executives are unable to resolve such Party’s concern the senior executives agree to instruct the Management Committee to negotiate a mutually agreeable reasonable wind down plan (which may include additional exit fees) to terminate the development relationship set forth in this Agreement. In the event of such termination, AMD shall be entitled to immediately exercise its rights in accordance with Section 8.9 below, subject to the payment terms of Section 5.8.a.

 

4.2

Each Party shall appoint a Pre-T0 Steering Committee member within thirty (30) days after the Effective Date. It is the intent of the Parties that Pre-T0 Steering Committee members be assigned to the Pre-T0 Activities for no less than two (2) year terms. The Pre-T0 Steering Committee members shall oversee Pre-T0 Activities and provide technical guidance to the Management Committee on Pre-T0 Activities definition. A Party may replace its Pre-T0 Steering Committee member, named below, by giving written notice to the other Party of such replacement. The responsibilities of the Pre-T0 Steering Committee members are set forth in Exhibit G.

 

The Pre-T0 Steering Committee is comprised initially of the following individuals:

 

 

***	Confidential Treatment Requested

 

4.3

Each Party shall appoint a Pre-T0 Project Leader within thirty (30) days after the Effective Date or in AMD’s case, a temporary Pre-T0 Project Leader, if needed, until an ongoing AMD Pre-T0 Project Leader is identified. It is the intent of the Parties that Pre-T0 Project Leaders be assigned to the Pre-T0 Activities for no less than two (2) year terms. The IBM Pre-T0 Project Leader shall be in charge of the day- to-day operations of the Pre-T0 Activities. A Party may replace its Pre-T0 Project Leader, named below, by giving written notice to the other Party of such replacement. The responsibilities of the Pre-T0 Project Leaders are set forth in Exhibit H.

 

The Pre-T0 Project Leaders shall be:

 

 

4.4

If Bump Technology is established as a Process Development Project, each Party shall appoint a Bump Technology Project Leader within thirty (30) days after the Effective Date. It is the intent of the Parties that Bump Technology Project Leaders be assigned to the Bump Technology Process Development Projects for no less than two (2) year terms. The IBM Project Leader shall be in charge of the day- to-day operations of the Bump Technology Process Development Projects. A Party may replace its Bump Technology Project Leader, named below, by giving written notice to the other Party of such replacement. The responsibilities of the Bump Technology Project Leaders are set forth in Exhibit I.

 

The Bump Technology Project Leaders shall be:

 

 

4.5

Each Party shall appoint a Project Leader within thirty (30) days after the Effective Date. It is the intent of the Parties that Project Leaders be assigned to the Process Development Projects for no less than two (2) year terms. The IBM Project Leader shall be in charge of the day- to-day operations of the Process Development Projects. A Party may replace its Project Leader, named below, by giving written notice to the other Party of such replacement. The responsibilities of the Project Leaders are set forth in Exhibit E.

 

***	Confidential Treatment Requested

 

The

Project Leaders shall be:

 

 

4.6

AMD will provide Representatives to work on the Process Development Projects and the Pre-T0 Activities at the Development Facilities. Exhibit C, attached hereto, shows the minimum staffing expected for such Representatives. If IBM so requests, AMD shall make a compensating payment to IBM at a rate of *** ($ *** ) U.S. Dollars per person month for each headcount below the minimum staffing level set forth in Exhibit C. AMD may, at its sole option, provide up to *** ( *** ) Representatives to work in the Development Facilities. The assignment of such Representatives shall be mutually agreed to by the Project Leaders

 

It is the intent of the Parties that such Representatives be assigned to the Process Development Projects, Pre-T0 Activities, development and other projects contemplated under this Agreement at the Development Facilities for no less than two (2) year terms. AMD may change the number of Representatives with a minimum of three (3) months prior written notice to the other Parties and may reassign Representatives with a minimum of one (1) month prior written notice to the other Parties.

 

The Parties will provide sufficient technical personnel on the Process Development Projects with the appropriate skills and experience to accomplish the Strategic Technology Objectives.

 

4.7	Each Party shall appoint a Technical Coordinator within thirty (30) days after the Effective Date. The Technical Coordinators shall be:

 

 

***	Confidential Treatment Requested

 

 

The Technical Coordinators shall be responsible for supervising exchanges of information among the Parties pursuant to Section 7.2, below. A Project Leader for a Party may replace the Technical Coordinator for such Party, named above, by giving written notice to the other Parties’ Project Leaders of such replacement.

 

4.8

Each Party agrees that its Representatives shall comply in all material respects with all personnel, human resources, security and safety rules, procedures and guidelines of the other Party applicable to contractors resident at or visiting the premises of such Party or its Subsidiary while such Representatives are on the other Party’s or its Subsidiary’s premises, including those set forth in Exhibit F. In particular, AMD agrees to abide by security requirements as may apply to their Representatives while at the Development Facilities. Each Party shall provide to the other in advance a set of documents setting forth all such rules, procedures and guidelines, including any updated versions thereof.

 

4.9

Each Party shall be responsible for the selection of its Representatives who will be assigned to work in the Development Facilities on the Process Development Projects. Personnel supplied by each Party who are Representatives of the supplying Party shall not for any purpose be considered employees or agents of any other Party. Each Party shall be responsible for the supervision, direction and control, payment of salary (including withholding of taxes), travel and living expenses (if any), worker’s compensation insurance, disability benefits and the like of its own Representatives. In addition, each Party may reassign any of its Representatives as such Party deems necessary, subject to Section 4.3, above.

 

4.10

If any Party should become aware of the existence of any hazardous conditions, property, or equipment which are under the control of another Party it shall so advise the other Party; however, it shall remain that Party’s responsibility to take all necessary precautions against injury to persons or damage to property from such hazards, property, or equipment until corrected by the other Party. Each Party agrees to comply with the Occupational Safety and Health Act (“OSHA”), applicable OSHA standards, applicable New York safety and health laws and regulations, any applicable municipal ordinances, and applicable facility safety rules of which the Party has notice, regarding the Representatives it assigns to the Process Development Project(s).

 

4.11	The Parties agree that the Parties and any Subsidiaries shall refrain from making any payment or gift of any value to any Representatives of any other Party assigned to the Development Facilities without the employing Party’s prior written approval. No Party (or

 

***	Confidential Treatment Requested

 

any of its Subsidiaries) may make any representation that might cause a Representative of another Party to believe that an employment relationship exists between such Representative and the other Party.

 

4.12	Each Party assumes no liability to the other Parties for any injury (including death) to persons or damage to or loss of property suffered on or about the Development Facilities unless caused by the gross misconduct or gross negligence of such Party, its Representatives or invitees.

 

4.13

To the extent permitted by law, during the term of this Agreement, each Party agrees neither to directly or indirectly solicit for employment purposes the Representatives of any other Party engaged in semiconductor development in IBM’s East Fishkill or Yorktown Research facilities or AMD’s Sunnyvale, Austin or Dresden facilities or other Representatives working on the Process Development Projects until at least one (1) year has passed between the date such employee stopped being engaged in semiconductor development, and the date of solicitation, without the prior written permission of such other Party. However, the foregoing does not preclude general (i.e., non-targeted) recruitment advertising. In addition, to the extent permitted by law, during the term of this Agreement, each Party agrees that its units, divisions, line of business or other comparable organizational structures, involved in the development of semiconductor process technologies shall not hire Representatives of any other Party engaged in the Process Development Projects, without the prior written permission of such other Party.

 

SECTION 5 - AMD FUNDING CONTRIBUTIONS AND ROYALTY PAYMENTS

 

5.1	AMD shall pay to IBM for the Term of this Agreement for its respective share of the costs of the Process Development Projects; such payments shall be made as follows (in millions of US dollars):

 

 

*

Notwithstanding the foregoing, if the Commencement Date is in the 3 rd calendar quarter of 2005, AMD will pay to IBM $*** (*** dollars) on or before September 30, 2005. Such payment will not be considered an overdue payment pursuant to Section 5.2. If the Commencement Date is in the 4 th calendar quarter of 2005, AMD’s 3 rd quarter 2005 payment above will be reduced to $ *** ( *** dollars), and the 4 th quarter 2005 payment will be increased to $ *** ( *** dollars), which amount will be payable on or before October 31, 2005. Such payment will not be considered an overdue payment pursuant to Section 5.2. For avoidance of doubt if the Commencement Date is in the 3 rd quarter of 2005, payments in

 

***	Confidential Treatment Requested

 

the 4 th quarter of 2005 and later will be made in accordance with Section 5.1 without this asterisked provision. For further avoidance of doubt if the Commencement Date is in the 4 th quarter of 2005, payments in 2006 and later will be made in accordance with Section 5.1 without this asterisked provision.

 

 

 

Through the term of this Agreement, AMD will pay IBM according to the tables above, where the applicable row of the table will be determined based upon the total number of partners, including IBM and AMD, participating in S Process Development in the Development Facilities. If the number of partners changes during the Term, then the new quarterly rate will take effect beginning in the quarter after such change in the number of partners occurs. The amounts described in this paragraph will be due in quarterly installments commencing with the first calendar quarter of 2006.

 

Such payments shall be made on the fifteenth of the first month of each calendar year quarter. This Agreement will serve as an invoice for such payments.

 

5.2

AMD shall be liable for interest on any overdue payment under this Agreement commencing on the date such payment becomes due at an annual rate equal to eighteen percent (18%) per year. If such interest rate exceeds the maximum legal rate in the jurisdiction where a claim therefor is being asserted, the interest rate shall be reduced to such maximum legal rate.

 

***	Confidential Treatment Requested

 

5.3

IBM shall apply the payments of Section 5.1 above towards Process Development Project costs and not for any license rights granted by any Party to any other Party for Background Know-How. Notwithstanding Section 5.1, AMD shall be required to share the incremental costs of any changes in scope in the Process Development Projects agreed to pursuant to Section 14.

 

5.4

Moreover, AMD shall pay IBM a royalty on all ASIC Products, at the rate of *** percent ( *** %) of the Net Selling Price of each unit of ASIC Product sold, leased or otherwise transferred directly or indirectly prior to five (5) years from *** for the technology used in said ASIC Product; provided that for ASIC Product using technology that did not complete T1 qualification (as set forth in Exhibit B) during the term of this Agreement, AMD shall not be liable for any royalty to IBM. It is expressly understood that all royalties for ASIC Products are paid on a per unit basis (e.g., Integrated Circuit or wafer) and no other royalties shall be due under this Agreement. Such royalty payments are to be paid by AMD for each ASIC Product sold, leased or otherwise transferred at the time of such sale, lease or transfer to a Third party. For clarity, such royalty obligation does not extend to transactions between or among the Parties and such Wholly Owned Subsidiaries or Related Subsidiaries that do not involve a Third Party. AMD shall pay IBM all royalties owed within forty-five (45) days after the end of each calendar quarter. AMD shall provide a royalty report to IBM within forty-five (45) days after the end of each calendar quarter. All payments shall be made by wire transfer to the IBM account listed in Section 13.1.1 below, in U.S. dollars. The following information shall be included in the wire detail:

 

Company Name

Reason for Payment

License Reference No. ***

 

5.5

AMD shall maintain a complete, clear and accurate record of the quantity of ASIC Products sold, leased or otherwise transferred and any other relevant information to the extent it is required to determine whether they are paying the correct royalty amount hereunder. To ensure compliance with the terms and conditions of this Agreement, IBM shall have the right to audit all relevant accounting and sales books and records of AMD. The audit will be conducted by a mutually acceptable audit firm, and shall be conducted following reasonable prior written notice (at least forty-five (45) days in advance) during regular business hours at an office where such records are normally maintained and in such a manner as not to interfere with AMD’s normal business activities and shall be restricted only to those records necessary to verify AMD’s obligations hereunder. The audit report provided to IBM may only include the information necessary to determine whether or not any underpayment or overpayment exists, and if it exists, the amount of such underpayment or overpayment. IBM shall instruct the auditor to include only business information in the audit report to IBM. IBM shall use the business information reported by the auditor only for the purpose of determining royalty payments and for no

 

***	Confidential Treatment Requested

 

other purpose. In no event shall audits be made hereunder more frequently than once in every twelve (12) months and the audit shall not cover any records from a period of time previously audited. If any audit should disclose any underpayment or overpayment, the owing Party shall within forty-five (45) days pay the difference. The cost of such audit will be borne by IBM. AMD shall be provided with a copy of the audit report within a reasonable period of time after its completion. The independent audit firm shall not be hired on a contingent fee basis and shall have confidentiality agreements in place sufficient to protect AMD’s confidential information.

 

5.6

If AMD exercises its option under Section 8.7, below, AMD agrees to pay IBM a royalty of (a)  *** ( *** ) percent for each 65nm SOI Wafer provided to, or purchased by, *** , and (b)  *** ( *** ) percent for each 45nm SOI Wafer and 32nm or 22nm AMD High Performance Integrated Circuit wafer provided to, or purchased by, a *** for the lesser of a period of four (4) years beginning on the initial date of *** of the applicable technology or the expiration of the confidentiality period for the applicable technology. If a *** is also a ***, the royalty rates will be *** (***) percent for 65 nm SOI Wafers and *** (***) percent for 45 nm SOI Wafers and 32nm or 22nm AMD High Performance Integrated Circuit wafers. The revenue basis for such qualified SOI Wafers and AMD High Performance Integrated Circuit wafers shall be the lesser of *** for processed SOI Wafers and AMD High Performance Integrated Circuit wafers of the respective technology generation. If AMD exercises its rights under the second paragraph of Section 8.7, then for the combined maximum capacity thereunder that IBM refuses pursuant to Section 8.7, AMD will pay IBM a royalty of *** percent for each SOI Wafer and *** percent of each Bulk CMOS wafer for 65 nm technology; *** percent for each SOI Wafer for 45nm and AMD High Performance Integrated Circuit wafer for 32nm or 22nm and *** percent for each Bulk CMOS wafer for 45 nm, and AMD Non-High Performance Integrated Circuit wafer for 32nm or 22nm technology provided to, or purchased by, a Third Party and the obligation to pay this royalty will terminate the lesser of